TRANSMISSION CHANNEL FOR ULTRASOUND APPLICATIONS
    11.
    发明公开
    TRANSMISSION CHANNEL FOR ULTRASOUND APPLICATIONS 审中-公开
    ÜBERTRAGUNGSKANALFÜRULTRASCHALLANWENDUNGEN

    公开(公告)号:EP3025792A1

    公开(公告)日:2016-06-01

    申请号:EP15196387.3

    申请日:2015-11-25

    CPC classification number: G05F3/02 B06B1/0215 H03K4/94 H03K17/162

    Abstract: A transmission channel transmits high-voltage pulses and receives echos of the high-voltage pulses. The transmission channel includes a current generator circuit (104), which generates current-integrator drive currents, a receiver (108), which amplifies transducer-echo signals, and control circuitry (102). The control circuitry generates one or more control signals to control generation of current-integrator drive currents by the current generator circuit during transducer-driving periods and reception of transducer-echo signals by the receiver during echo-reception periods. A current integrator (106) integrates current-integrator drive currents generated by current generator circuit to generate transducer drive signals.

    Abstract translation: 传输通道传输高电压脉冲并接收高电压脉冲的回波。 传输通道包括产生电流积分器驱动电流的电流发生器电路(104),放大换能器回波信号的接收器(108)和控制电路(102)。 控制电路产生一个或多个控制信号,以在换能器驱动周期期间由电流发生器电路控制电流积分器驱动电流的产生,并且在回波接收周期期间由接收器接收换能器 - 回波信号。 电流积分器(106)集成由电流发生器电路产生的电流积分器驱动电流以产生换能器驱动信号。

    HIGH VOLTAGE SWITCH CONFIGURATION
    12.
    发明公开
    HIGH VOLTAGE SWITCH CONFIGURATION 审中-公开
    高压开关配置

    公开(公告)号:EP2489126A1

    公开(公告)日:2012-08-22

    申请号:EP10776932.5

    申请日:2010-10-18

    CPC classification number: H03K17/063

    Abstract: The invention relates to a High Voltage switch configuration (10) having an input terminal (IN) which receives an input signal (Vin) to drive a load and an output terminal (OUT) which issues an output signal (Vout) to the load. Advantageously according to the invention, the High Voltage switch configuration ( 10) comprises at least a first and a second diode (D1, D2), being placed in antiseries between said input and output terminals (IN, OUT) and having a pair of corresponding terminals in common, in correspondence of a first internal circuit node (Xc1).

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