公开(公告)号：EP1612950A1

公开(公告)日：2006-01-04

申请号：EP04425486.0

申请日：2004-06-30

Applicant: STMicroelectronics S.r.l.

Inventor： Marelli, Alessia ,  Ravasio, Roberto ,  Micheloni, Rino

IPC: H03M13/15 ,  G06F11/10

CPC classification number: H03M13/1555 ,  H03M13/152 ,  H03M13/6561

Abstract: The invention relates to a method and system for correcting errors in multilevel memories, both of the NAND and of the NOR type. The method provides the use of a BCH correction code made parallel by means of a coding and decoding architecture allowing the latency limits of prior art sequential solutions to be overcome. Two possible solutions are shown.
The parallelism being used for blocks C, 1 and 3 can be chosen in order to optimise the system performances in terms of latency and device area.

Abstract translation: 本发明涉及一种方法和系统，用于多级存储器校正错误，这两种类型的NAND和NOR。 该方法提供使用的BCH纠错码由编码和解码架构，允许现有技术解决方案的顺序的延迟限制的方式作出平行于被克服。 两种可能的解决方案中。 正在使用的并行用于块C，1和3可以以优化系统性能的延迟和设备面积方面进行选择。

公开(公告)号：EP1460765A1

公开(公告)日：2004-09-22

申请号：EP03425172.8

申请日：2003-03-19

Applicant: STMicroelectronics S.r.l.

Inventor： Lunelli, Massimiliano ,  Micheloni, Rino ,  Ravasio, Roberto ,  Marelli, Alessia

IPC: H03M13/13 ,  H03M13/15 ,  H03M13/19

CPC classification number: H03M13/1575 ,  H03M13/13 ,  H03M13/15 ,  H03M13/19

Abstract: A method for making error corrections on digital information coded as symbol sequences ( x ), for example digital information stored in electronic memory systems or transmitted from and to these systems is described, providing the transmission of sequences ( x ) incorporating a portion of error corrector code allowing the sequence ( x ) which is more probably the original transmitted through the calculation of an error syndrome using a parity matrix to be restored when received.
Advantageously according to the invention, the error code incorporated in the original sequence ( x ) belongs to a non Boolean group.

Abstract translation: 描述了用于对编码为符号序列（x）的数字信息进行纠错的方法，例如存储在电子存储器系统中或从这些系统发送的数字信息，或从这些系统发送和传送到这些系统的方法，提供包含错误校正器的一部分的序列（x） 允许更可能是通过使用奇偶校验矩阵计算误差校正子传送的序列（x）的序列（x），以便在接收时恢复。 有利地，根据本发明，并入原始序列（x）中的错误代码属于非布尔组。

公开(公告)号：EP1830269B1

公开(公告)日：2009-05-13

申请号：EP06425141.6

申请日：2006-03-02

Applicant: STMicroelectronics S.r.l.

Inventor： Marelli, Alessia ,  Intini, Valeria ,  Ravasio, Roberto ,  Micheloni, Rino

IPC: G06F11/10 ,  G06F11/14

CPC classification number: G06F11/1076 ,  G06F11/1068 ,  G06F11/141 ,  G11B20/18

公开(公告)号：EP1635261B1

公开(公告)日：2008-06-11

申请号：EP04425678.2

申请日：2004-09-10

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Micheloni, Rino ,  Ravasio, Roberto ,  Bovino, Angelo ,  Altieri, Vincenzo

IPC: G06F11/10

CPC classification number: G06F11/1048

公开(公告)号：EP1830269A1

公开(公告)日：2007-09-05

申请号：EP06425141.6

申请日：2006-03-02

Applicant: STMicroelectronics S.r.l.

Inventor： Marelli, Alessia ,  Intini, Valeria ,  Ravasio, Roberto ,  Micheloni, Rino

IPC: G06F11/10 ,  G06F11/14

CPC classification number: G06F11/1076 ,  G06F11/1068 ,  G06F11/141 ,  G11B20/18

Abstract: A reading method for a memory device with error-correcting encoding envisages the steps of: carrying out a first reading of a plurality of memory locations (A 0 , A 1 , ..., A LS-1 ) to generate a first recovered string (S 1 ), and performing a first decoding attempt using the first recovered string (S 1 ). When the first decoding attempt fails, the memory locations are read at least one second time, and at least one second recovered string (S 2 -S N ) is generated. On the basis of a comparison between the first recovered string (S 1 ) and the second recovered string (S 2 -S N ), a modified string (S M ) is generated, in which erasures (X) are located, and at least one second decoding attempt is carried out using the modified string (S M ).

Abstract translation: 用于与错误校正编码的存储器装置的读出方法设想如下步骤：执行的存储器位置处的多个第一读取（A 0，A 1，...，A LS-1），以产生一个第一回收串 （S 1），并执行使用第一回收串（S 1）的第一解码尝试。 当第一解码尝试失败，存储器位置被读取的至少一个第二时间，并且至少一个第二回收串（S 2 -S N）被产生。 在第一回收串（S 1）和所述第二回收串（S 2 -S N）之间的比较的基础上，产生一个修改后的字符串（SM），其中擦除（X）的位置，和至少一个第二 解码尝试是使用修改后的字符串（SM）。

公开(公告)号：EP1420415A3

公开(公告)日：2007-02-28

申请号：EP03104130.4

申请日：2003-11-10

Applicant: STMicroelectronics S.r.l.

Inventor： Micheloni, Rino ,  Ravasio, Roberto

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C16/30

Abstract: A circuit (115,145,150) for programming a non-volatile memory device (100) having a plurality of memory cells (105) is proposed. The circuit includes a plurality of driving elements (115) each one for applying a program pulse to a selected memory cell to be programmed, the driving elements being suitable to be supplied by a power supply unit (120,125), and control means (145,150) for controlling the driving elements; the control means includes means (150,205) for determining a residual capacity of the power supply unit, and selecting means (145) for selectively enabling the driving elements according to the residual capacity.

公开(公告)号：EP1748446A1

公开(公告)日：2007-01-31

申请号：EP05106975.5

申请日：2005-07-28

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Micheloni, Rino ,  Crippa, Luca ,  Ravasio, Roberto

IPC: G11C11/56

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/3436 ,  G11C2211/5621 ,  G11C2211/5642

Abstract: A method for programming an electrically programmable memory (100) is provided. The electrically programmable memory includes a plurality of memory cells (110) arranged in individually-selectable memory cell sets each including at least one memory cell, a plurality of distinct memory cell programming states (201, 202, 203, 204) corresponding to a number N >=2 of data bits storable in each memory cell. The data bits include at least a first data bits group (LSB) and a second data bits group (MSB); the first data bits groups and, respectively, the second data bits groups stored in the memory cells of one of said individually-selectable memory cell sets form at least a first memory page and a second memory page, respectively, the first and second memory pages being individually addressable.
The programming method comprises:
- causing the memory cells of a selected memory cells set to be brought into a predetermined, starting programming state (201);
- receiving a target value for the first data bits groups of the memory cells of the selected memory cells set;
- receiving a target value for the second data bits groups of the memory cells of the selected memory cells set;
- after having received the target values of both the first and the second data bits groups, applying to the memory cells of the selected memory cells set a programming sequence (350) adapted to cause the memory cells of the selected memory cells sets to be brought into a target programming state (201,202,203,204) jointly determined by the target values of the first and second data bits groups.

Abstract translation: 提供了一种用于编程电可编程存储器（100）的方法。 电可编程存储器包括布置在可单独选择的存储单元组中的多个存储单元（110），每个存储单元组包括至少一个存储单元，多个不同的存储单元编程状态（201,202,203,204） N> = 2可存储在每个存储单元中的数据位。 数据位包括至少第一数据位组（LSB）和第二数据位组（MSB）; 第一数据位组和分别存储在所述可单独选择的存储单元组之一的存储单元中的第二数据位组分别形成至少第一存储器页和第二存储器页，第一和第二存储器页 单独寻址。 编程方法包括： - 使所设置的选定存储单元的存储单元进入预定的开始编程状态（201）; - 接收所选存储单元组的存储单元的第一数据位组的目标值; - 接收所选存储单元组的存储单元的第二数据位组的目标值; - 在已经接收到第一和第二数据位组之间的目标值之后，向所选择的存储单元的存储单元施加设置适于使所选择的存储单元组的存储单元被带入的编程序列（350） 转换为由第一和第二数据位组的目标值共同确定的目标编程状态（201,202,203,204）。

公开(公告)号：EP1612949A1

公开(公告)日：2006-01-04

申请号：EP04425485.2

申请日：2004-06-30

Applicant: STMicroelectronics S.r.l.

Inventor： Marelli, Alessia ,  Ravasio, Roberto ,  Micheloni, Rino

IPC: H03M13/15 ,  G06F11/10

CPC classification number: H03M13/152 ,  H03M13/1575 ,  H03M13/3707 ,  H03M13/6502

Abstract: The invention relates to a method and system for correcting errors in multilevel memories using binary BCH codes. The number of errors is estimated by analyzing the syndrome components (5). If the number of estimated errors is one, then simple decoding for a Hamming code is performed. Otherwise, conventional decoding of the BCH code is carried out (2,3). This avoids the computation of the error locator polynomial and its roots in the presence of only one error and, thus, reduces the average decoding complexity.

Abstract translation: 本发明涉及一种使用二进制BCH码对多层存储器中的错误进行校正的方法和系统。 通过分析综合征成分估计误差数（5）。 如果估计误差的数量为1，则执行汉明码的简单解码。 否则，执行BCH码的常规解码（2,3）。 这避免了在仅存在一个错误的情况下计算错误定位器多项式及其根，并因此降低平均解码复杂度。

公开(公告)号：EP1420415A2

公开(公告)日：2004-05-19

申请号：EP03104130.4

申请日：2003-11-10

Applicant: STMicroelectronics S.r.l.

Inventor： Micheloni, Rino ,  Ravasio, Roberto

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C16/30

Abstract: A circuit (115,145,150) for programming a non-volatile memory device (100) having a plurality of memory cells (105) is proposed. The circuit includes a plurality of driving elements (115) each one for applying a program pulse to a selected memory cell to be programmed, the driving elements being suitable to be supplied by a power supply unit (120,125), and control means (145,150) for controlling the driving elements; the control means includes means (150,205) for determining a residual capacity of the power supply unit, and selecting means (145) for selectively enabling the driving elements according to the residual capacity.

Abstract translation: 提出了一种用于对具有多个存储单元（105）的非易失性存储器件（100）进行编程的电路（115,145,150）。 电路包括多个驱动元件（115），每个驱动元件（115）用于将编程脉冲施加到要被编程的所选择的存储器单元，所述驱动元件适于由电源单元（120,125）提供;以及控制装置（145,150） 用于控制驱动元件; 所述控制装置包括用于确定所述电源单元的剩余容量的装置（150,205），以及用于根据所述剩余容量选择性地启用所述驱动元件的选择装置（145）。

公开(公告)号：EP1909290B1

公开(公告)日：2009-10-07

申请号：EP06119452.8

申请日：2006-08-24

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Micheloni, Rino ,  Crippa, Luca ,  Ravasio, Roberto ,  Pio, Federico

IPC: G11C16/34

CPC classification number: G11C16/344