公开(公告)号：EP1610343B1

公开(公告)日：2007-12-19

申请号：EP04102942.2

申请日：2004-06-24

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Zanardi, Stefano ,  Martinozzi, Giulio

IPC: G11C16/10 ,  G11C16/26

CPC classification number: G11C16/26 ,  G11C16/10 ,  G11C2216/14

公开(公告)号：EP1598831B1

公开(公告)日：2007-11-21

申请号：EP04102232.8

申请日：2004-05-20

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Khouri, Osama ,  Zanardi, Stefano ,  Martinozzi, Giulio

IPC: G11C16/10 ,  G11C16/26

CPC classification number: G11C16/26

公开(公告)号：EP0821484B1

公开(公告)日：2002-10-09

申请号：EP96830413.9

申请日：1996-07-24

Applicant: STMicroelectronics S.r.l.

Inventor： Campardo, Giovanni ,  Zanardi, Stefano ,  Golla, Carla

IPC: H03K17/00 ,  H03K19/003

CPC classification number: H03K19/00315 ,  H03K19/00384

公开(公告)号：EP0911974A1

公开(公告)日：1999-04-28

申请号：EP97830542.3

申请日：1997-10-24

Applicant: STMicroelectronics S.r.l.

Inventor： Mulatti, Jacopo ,  Zanardi, Stefano ,  Golla, Carla Maria ,  Conci, Armando

IPC: H03K19/003

CPC classification number: H01L27/0928 ,  H01L27/0251 ,  H03K17/162 ,  H03K19/00361 ,  Y10S257/901

Abstract: Output circuit for an integrated circuit, comprising first transistor means (P2) and second transistor means (N2) connected in series between a first external voltage (Vcc) and a second external voltage (Gnd) external to the integrated circuit (100), respectively through first (L2) and second electrical connecting means (L4). The first transistor means for carry an output line (5) of the integrated circuit to the first external voltage, while the second transistor means for carry said external line of the integrated circuit to said second external voltage. The second transistor means are formed inside a first well (130) of a first conductivity type contained inside a second well (140) of a second conductivity type formed in a substrate (7) of the first conductivity type. The second well (140) of the second conductivity type is connected to said first external voltage (Vcc) through third electrical connecting means (L21) distinct from said first electrical connecting means (L2).

Abstract translation: 一种用于集成电路的输出电路，包括分别串联在集成电路（100）外部的第一外部电压（Vcc）和第二外部电压（Gnd）之间的第一晶体管装置（P2）和第二晶体管装置（N2） 通过第一（L2）和第二电连接装置（L4）。 第一晶体管用于将集成电路的输出线（5）传送到第一外部电压，而第二晶体管用于将集成电路的所述外部线路传送到所述第二外部电压。 第二晶体管装置形成在形成在第一导电类型的衬底（7）中的第二导电类型的第二阱（140）内的第一导电类型的第一阱（130）内。 第二导电类型的第二阱（140）通过与所述第一电连接装置（L2）不同的第三电连接装置（L21）连接到所述第一外部电压（Vcc）。