公开(公告)号：US10971451B2

公开(公告)日：2021-04-06

申请号：US16215899

申请日：2018-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun Byun ,  Keunwook Shin ,  Yonghoon Kim ,  Hyeonjin Shin ,  Hyunjae Song ,  Changseok Lee ,  Changhyun Kim ,  Yeonchoo Cho

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: Provided are an interconnect structure and an electronic device including the interconnect structure. The interconnect structure includes a dielectric layer including at least one trench, a conductive wiring filling an inside of the at least one trench, and a cap layer on at least one surface of the conductive wiring. The cap layer includes nanocrystalline graphene. The nanocrystalline includes nano-sized crystals.

公开(公告)号：US10727182B2

公开(公告)日：2020-07-28

申请号：US16257189

申请日：2019-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae Song ,  Seunggeol Nam ,  Yeonchoo Cho ,  Seongjun Park ,  Hyeonjin Shin ,  Jaeho Lee

IPC: H01L23/48 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: Example embodiments relate to a layer structure having a diffusion barrier layer, and a method of manufacturing the same. The layer structure includes first and second material layers and a diffusion barrier layer therebetween. The diffusion barrier layer includes a nanocrystalline graphene (nc-G) layer. In the layer structure, the diffusion barrier layer may further include a non-graphene metal compound layer or a graphene layer together with the nc-G layer. One of the first and second material layers is an insulating layer, a metal layer, or a semiconductor layer, and the remaining layer may be a metal layer.

公开(公告)号：US20200039827A1

公开(公告)日：2020-02-06

申请号：US16233513

申请日：2018-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Alum JUNG ,  Keunwook Shin ,  Kyung-Eun Byun ,  Hyeonjin Shin ,  Hyunseok Lim ,  Seunggeol Nam ,  Hyunjae Song ,  Yeonchoo Cho

IPC: C01B32/186 ,  C23C16/26 ,  C23C16/505 ,  C23C16/511 ,  H01L21/02 ,  H01L29/16 ,  H01L29/06 ,  H01L29/04

Abstract: A method of forming nanocrystalline graphene by a plasma-enhanced chemical vapor deposition process is provided. The method of forming nanocrystalline graphene includes arranging a protective layer on a substrate and growing nanocrystalline graphene directly on the protective layer by using a plasma of a reaction gas. The reaction gas may include a mixed gas of a carbon source gas, an inert gas, and hydrogen gas.

公开(公告)号：US10134628B2

公开(公告)日：2018-11-20

申请号：US15172908

申请日：2016-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae Song ,  Seunggeol Nam ,  Seongjun Park ,  Keunwook Shin ,  Hyeonjin Shin ,  Jaeho Lee ,  Changseok Lee ,  Yeonchoo Cho

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/485 ,  H01L21/285 ,  H01L29/45

Abstract: A multilayer structure includes a first material layer, a second material layer, and a diffusion barrier layer. The second material layer is connected to the first material layer. The second material layer is spaced apart from the first material layer. The diffusion barrier layer is between the first material layer and the second material layer. The diffusion barrier layer may include a two-dimensional (2D) material. The 2D material may be a non-graphene-based material, such as a metal chalcogenide-based material having a 2D crystal structure. The first material layer may be a semiconductor or an insulator, and the second material layer may be a conductor. At least a part of the multilayer structure may constitute an interconnection for an electronic device.

公开(公告)号：US12002882B2

公开(公告)日：2024-06-04

申请号：US18157478

申请日：2023-01-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun Lee ,  Minsu Seol ,  Yeonchoo Cho ,  Hyeonjin Shin

IPC: H01L29/778 ,  H01L27/092 ,  H01L29/24 ,  H01L29/417 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/7788 ,  H01L27/092 ,  H01L29/24 ,  H01L29/41741 ,  H01L29/7831 ,  H01L29/78642

Abstract: A vertical type transistor includes: a substrate; a first source/drain electrode layer provided on the substrate; a second source/drain electrode layer provided above the first source/drain electrode layer; a first gate electrode layer provided between the first and second source/drain electrode layers; a first gate insulating film passing through the first gate electrode layer; a hole passing through the second source/drain electrode layer, the first gate insulating film, and the first source/drain electrode layer; and a first channel layer provided on a lateral side of the hole, wherein the first channel layer may include a 2D semiconductor.

公开(公告)号：US11961898B2

公开(公告)日：2024-04-16

申请号：US17546303

申请日：2021-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Van Luan Nguyen ,  Minsu Seol ,  Junyoung Kwon ,  Hyeonjin Shin ,  Minseok Yoo ,  Yeonchoo Cho

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/304 ,  H01L21/463

CPC classification number: H01L29/66045 ,  H01L21/02488 ,  H01L21/02491 ,  H01L21/02527 ,  H01L21/02568 ,  H01L21/304 ,  H01L21/463 ,  H01L29/66969

Abstract: A method of patterning a 2D material layer is includes selectively forming a first material layer on a surface of a substrate to form a first region in which the first material layer covers the surface of the substrate and to further form a second region in which the surface of the substrate is exposed from the first material layer, the first material layer having a strong adhesive force with a 2D material. The method further includes forming a 2D material layer is formed in both the first region and the second region. The method further includes selectively removing the 2D material layer from the second region based on using a physical removal method, such that the 2D material layer remains in the first region.

公开(公告)号：US20230253320A1

公开(公告)日：2023-08-10

申请号：US18297852

申请日：2023-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjin SHIN ,  Sangwon Kim ,  Kyung-Eun Byun ,  Hyunijae Song ,  Keunwook Shin ,  Eunkyu Lee ,  Changseok Lee ,  Yeonchoo Cho ,  Taejin Choi

IPC: H01L23/528 ,  H10B53/30

CPC classification number: H01L23/5283 ,  H10B53/30

Abstract: An interconnect structure for reducing a contact resistance, an electronic device including the same, and a method of manufacturing the interconnect structure are provided. The interconnect structure includes a semiconductor layer including a first region having a doping concentration greater than a doping concentration of the rest region of the semiconductor layer, a metal layer facing the semiconductor layer, a semi-metal layer between the semiconductor layer and the metal layer, and a conductive metal oxide layer between the semi-metal layer and the semiconductor and covering the first region.

公开(公告)号：US11588034B2

公开(公告)日：2023-02-21

申请号：US17060696

申请日：2020-10-01

Applicant: Samsung Electronics Co., Ltd. ,  SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

Inventor： Minhyun Lee ,  Minsu Seol ,  Ho Won Jang ,  Yeonchoo Cho ,  Hyeonjin Shin

IPC: H01L29/423 ,  H01L29/04 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66

Abstract: Provided is a field effect transistor including a gate insulating layer having a two-dimensional material. The field effect transistor may include a first channel layer; a second channel layer disposed on the first channel layer; a gate insulating layer disposed on the second channel layer; a gate electrode disposed on the gate insulating layer; a first electrode electrically connected to the first channel layer; and a second electrode electrically connected to the second channel layer. Here, the gate insulating layer may include an insulative, high-k, two-dimensional material.

公开(公告)号：US11572278B2

公开(公告)日：2023-02-07

申请号：US16675350

申请日：2019-11-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjin Shin ,  Keunwook Shin ,  Changhyun Kim ,  Seunggeol Nam ,  Kyung-Eun Byun ,  Hyunjae Song ,  Eunkyu Lee ,  Changseok Lee ,  Alum Jung ,  Yeonchoo Cho

IPC: B32B9/00 ,  C01B32/186 ,  B82Y30/00

Abstract: A method of growing graphene includes forming a carbon monolayer on a substrate by injecting a first reaction gas into a reaction chamber, wherein the first reaction gas includes a first source including a component that is a carbon source and belongs to an electron withdrawing group, and injecting a second reaction gas including a second source into the reaction chamber, wherein the second source includes a functional group that forms a volatile structure by reacting with a component that belongs to an electron withdrawing group. Graphene may be directly grown on a surface of the substrate by repeatedly injecting the first reaction gas and the second reaction gas.

公开(公告)号：US11563116B2

公开(公告)日：2023-01-24

申请号：US17201485

申请日：2021-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun Lee ,  Minsu Seol ,  Yeonchoo Cho ,  Hyeonjin Shin

IPC: H01L29/778 ,  H01L29/24 ,  H01L29/786 ,  H01L29/417 ,  H01L27/092 ,  H01L29/78

Abstract: A vertical type transistor includes: a substrate; a first source/drain electrode layer provided on the substrate; a second source/drain electrode layer provided above the first source/drain electrode layer; a first gate electrode layer provided between the first and second source/drain electrode layers; a first gate insulating film passing through the first gate electrode layer; a hole passing through the second source/drain electrode layer, the first gate insulating film, and the first source/drain electrode layer; and a first channel layer provided on a lateral side of the hole, wherein the first channel layer may include a 2D semiconductor.