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    Peripheral Watchdog Timer
    11.
    发明申请
    Peripheral Watchdog Timer 有权
    外设看门狗定时器

    公开(公告)号：US20160335149A1

    公开(公告)日：2016-11-17

    申请号：US14709204

    申请日：2015-05-11

    Applicant: Silicon Laboratories Inc.

    Inventor： Thomas Saroshan David

    IPC: G06F11/07

    CPC classification number: G06F11/0757 ,  G06F11/00 ,  G06F11/0706

    Abstract: In some embodiments, a circuit may include a plurality of peripherals and a peripheral watchdog timer circuit coupled to at least one of the plurality of peripherals. The peripheral watchdog timer circuit may be configured to count clock cycles and concurrently to detect activity associated with at least one of the plurality of peripherals. The peripheral watchdog timer circuit may be configured to reset a count in response to detecting the activity. In some embodiments, the peripheral watchdog timer circuit may be configured to generate an alert signal when the count exceeds a threshold count before detecting the activity. In some embodiments, the peripheral watchdog timer circuit is configured to initiate a reset operation when the alert is not serviced within a period of time.

    Abstract translation: 在一些实施例中，电路可以包括耦合到多个外围设备中的至少一个外围设备的多个外围设备和外围看门狗定时器电路。 周边看门狗定时器电路可以被配置为对时钟周期进行计数并且同时地检测与多个外围设备中的至少一个相关联的活动。 外围看门狗定时器电路可以被配置为响应于检测到活动来重置计数。 在一些实施例中，外围看门狗定时器电路可以被配置为当在检测到活动之前计数超过阈值计数时产生警报信号。 在一些实施例中，周边看门狗定时器电路被配置为当在一段时间内未提醒警报时启动复位操作。

    Flip-flop with input and output select and output masking that enables low power scan for retention
    12.
    发明授权
    Flip-flop with input and output select and output masking that enables low power scan for retention 有权

    公开(公告)号：US11750178B2

    公开(公告)日：2023-09-05

    申请号：US17517054

    申请日：2021-11-02

    Applicant: Silicon Laboratories Inc.

    Inventor： Thomas Saroshan David

    IPC: H03K3/356 ,  H03K3/012 ,  H03K3/037

    CPC classification number: H03K3/356121 ,  H03K3/012 ,  H03K3/0375

    Abstract: A flip-flop including a scan enable input for receiving a scan enable signal, a clock input for receiving a clock signal, input select circuitry that is configured to select between a data input and a scan input based on a state of the scan enable signal for providing a selected input, latching circuitry that is configured to latch the selected input to a preliminary output node in response to transitions of the clock signal, and output select circuitry that is configured to provide a state of the preliminary output node to a selected one of a scan output and a data output based on a state of the scan enable signal. The flip-flop may be implemented using fast yet leaky transistors. The data output may be disabled to prevent toggling other circuitry when scanning into or out of a memory for data retention.

    High-speed synchronizer with lower metastability failure rate
    13.
    发明授权
    High-speed synchronizer with lower metastability failure rate 有权

    公开(公告)号：US11133921B1

    公开(公告)日：2021-09-28

    申请号：US16942484

    申请日：2020-07-29

    Applicant: Silicon Laboratories Inc.

    Inventor： Linxiao Shen ,  Thomas Saroshan David

    IPC: H04L7/00

    Abstract: A data synchronizer including an input stage, a driver stage, and a keeper stage. The input stage latches input data to a data node in response to a first clock signal transition. The driver stage has an input coupled to the data node and has an output coupled to a gain node. The keeper stage latches data asserted on the gain node back to the input stage to maintain data on the data node in response to a second transition of the clock signal. The driver stage has an increased drive strength and a reduced loading capacitance to increase the gain-bandwidth product of the latch loop to reduce metastability. A flip-flop may be configured with input and output latches each including driver stages having increased drive strength and reduced loading capacitance to increase the gain-bandwidth product of each of the latch loops to reduce metastability.

    Apparatus with write-back buffer and associated methods
    15.
    发明授权
    Apparatus with write-back buffer and associated methods 有权
    具有回写缓冲器和相关方法的设备

    公开(公告)号：US09378782B1

    公开(公告)日：2016-06-28

    申请号：US14720811

    申请日：2015-05-24

    Applicant: Silicon Laboratories Inc.

    Inventor： Thomas Saroshan David

    IPC: G11C7/10

    CPC classification number: G11C7/22 ,  G06F11/1048 ,  G11C7/1006 ,  G11C7/1087 ,  G11C11/005 ,  G11C2207/2245 ,  G11C2207/229

    Abstract: An apparatus comprises a source to communicate data, and a storage circuit to store data communicated by the source. The apparatus further comprises a write-back buffer to store data communicated by the source in a misaligned write operation in order to improve throughput between the source and the storage circuit.

    Abstract translation: 一种装置包括用于传送数据的源，以及存储电路，用于存储由源传送的数据。 该装置还包括一个回写缓冲器，用于存储由源在不对齐的写入操作中传送的数据，以便提高源和存储电路之间的吞吐量。

    Low-Power Communication Apparatus with Wakeup Detection and Associated Methods
    16.
    发明申请
    Low-Power Communication Apparatus with Wakeup Detection and Associated Methods 审中-公开
    具有唤醒检测和相关方法的低功率通信设备

    公开(公告)号：US20160018873A1

    公开(公告)日：2016-01-21

    申请号：US14869926

    申请日：2015-09-29

    Applicant: Silicon Laboratories Inc.

    Inventor： Kenneth W. Fernald ,  Thomas Saroshan David

    IPC: G06F1/32

    Abstract: An apparatus includes a communication circuit coupled to a communication link, a wakeup detector, and a power control circuit. The communication circuit has a first state and a second state. The power consumption of the communication circuit is lower in the second state than in the first state. The wakeup detector is coupled to the communication link. The wakeup detector generates a wakeup signal to cause the communication circuit to make a transition from the second state to the first state in response to an occurrence of an event on the communication link. The power control circuit selectively supplies power to the communication circuit in response to the wakeup signal.

    Abstract translation: 一种装置包括耦合到通信链路的通信电路，唤醒检测器和功率控制电路。 通信电路具有第一状态和第二状态。 通信电路的功耗在第二状态下低于第一状态。 唤醒检测器耦合到通信链路。 唤醒检测器响应于通信链路上的事件的发生而产生唤醒信号以使通信电路从第二状态转变到第一状态。 功率控制电路响应于唤醒信号选择性地向通信电路供电。

    Interface between Processing Unit and an External Nonvolatile Memory
    17.
    发明公开
    Interface between Processing Unit and an External Nonvolatile Memory 审中-公开

    公开(公告)号：US20230305983A1

    公开(公告)日：2023-09-28

    申请号：US17700907

    申请日：2022-03-22

    Applicant: Silicon Laboratories Inc.

    Inventor： Aslam Rafi ,  Thomas Saroshan David ,  Daniel Cooley

    IPC: G06F13/40 ,  G06F1/12

    CPC classification number: G06F13/4068 ,  G06F1/12

    Abstract: An interface between two devices is disclosed. To consume power, the signals used in the interface utilize CMOS signalling. Further, to achieve high speed, a reduced frequency clock is transmitted from one device to the second device. The second device has a clock multiplier to recreate the original clock. Both devices utilize a clock phase alignment block which aligns the phase of the clock with the incoming data. The clock phase alignment block utilizes a digital PLL to consume power. Further, since the digital PLL retains its state, the reduced frequency clock may be disabled when data is not being transmitted. This interface may be used to transmit serial data at rates up to and exceeding 2.5 Gbits/sec.

    External Nonvolatile Memory with Additional Functionality
    18.
    发明公开
    External Nonvolatile Memory with Additional Functionality 审中-公开

    公开(公告)号：US20230305737A1

    公开(公告)日：2023-09-28

    申请号：US17700906

    申请日：2022-03-22

    Applicant: Silicon Laboratories Inc.

    Inventor： Thomas Saroshan David ,  Aslam Rafi ,  Joshua Norem ,  Adrianus Josephus Bink ,  Daniel Cooley

    IPC: G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0613 ,  G06F3/0622 ,  G06F3/0679

    Abstract: An external nonvolatile memory device that includes a rewritable nonvolatile memory and a CMOS interface is disclosed. The interface includes a clock signal which is input to the external nonvolatile memory device. This clock signal is multiplied by an integer to create a memory serdes clock which is used to clock outgoing data. The memory serdes clock is also used to create a clock that is used to clock the incoming data from the main processing device. The external nonvolatile memory device also includes an encryption/decryption block that encrypts data read from the nonvolatile memory before it is transmitted over the interface, and decrypts data received from the interface before storing it in the nonvolatile memory. The encryption/decryption block may utilize a stream cipher.

    FLIP-FLOP WITH INPUT AND OUTPUT SELECT AND OUTPUT MASKING THAT ENABLES LOW POWER SCAN FOR RETENTION
    19.
    发明申请
    FLIP-FLOP WITH INPUT AND OUTPUT SELECT AND OUTPUT MASKING THAT ENABLES LOW POWER SCAN FOR RETENTION 有权

    公开(公告)号：US20230133269A1

    公开(公告)日：2023-05-04

    申请号：US17517054

    申请日：2021-11-02

    Applicant: Silicon Laboratories Inc.

    Inventor： Thomas Saroshan David

    IPC: H03K3/356 ,  H03K3/037 ,  H03K3/012

    Abstract: A flip-flop including a scan enable input for receiving a scan enable signal, a clock input for receiving a clock signal, input select circuitry that is configured to select between a data input and a scan input based on a state of the scan enable signal for providing a selected input, latching circuitry that is configured to latch the selected input to a preliminary output node in response to transitions of the clock signal, and output select circuitry that is configured to provide a state of the preliminary output node to a selected one of a scan output and a data output based on a state of the scan enable signal. The flip-flop may be implemented using fast yet leaky transistors. The data output may be disabled to prevent toggling other circuitry when scanning into or out of a memory for data retention.

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