公开(公告)号：US20230305737A1

公开(公告)日：2023-09-28

申请号：US17700906

申请日：2022-03-22

Applicant: Silicon Laboratories Inc.

Inventor： Thomas Saroshan David ,  Aslam Rafi ,  Joshua Norem ,  Adrianus Josephus Bink ,  Daniel Cooley

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0613 ,  G06F3/0622 ,  G06F3/0679

Abstract: An external nonvolatile memory device that includes a rewritable nonvolatile memory and a CMOS interface is disclosed. The interface includes a clock signal which is input to the external nonvolatile memory device. This clock signal is multiplied by an integer to create a memory serdes clock which is used to clock outgoing data. The memory serdes clock is also used to create a clock that is used to clock the incoming data from the main processing device. The external nonvolatile memory device also includes an encryption/decryption block that encrypts data read from the nonvolatile memory before it is transmitted over the interface, and decrypts data received from the interface before storing it in the nonvolatile memory. The encryption/decryption block may utilize a stream cipher.

公开(公告)号：US20230418603A1

公开(公告)日：2023-12-28

申请号：US17846587

申请日：2022-06-22

Applicant: Silicon Laboratories Inc.

Inventor： Marius Grannaes ,  Joshua Norem

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30036 ,  G06F9/3816 ,  G06F9/3004 ,  G06F9/30112

Abstract: A system for securing the contents of an external nonvolatile memory associated with a main processing device is disclosed. The system stores additional information associated with each cache line in the nonvolatile memory. In some embodiments, this additional information comprises a NONCE (number used once) and a MAC (Message Authentication Code). When the main processing device reads a cache line from the nonvolatile memory, the NONCE, address and data from the cache line are used to generate a MAC, which is then compared to the MAC stored in the nonvolatile memory. If the MACs match, the cache line is stored in the on-board cache of the main processing device. If the MACs do not match, a countermeasure may be implemented. The use of a NONCE addresses an information leakage issue that is present when stream ciphers, such as AES-CTR or AES-GCM, are used in data storage applications.

公开(公告)号：US12175118B2

公开(公告)日：2024-12-24

申请号：US17700906

申请日：2022-03-22

Applicant: Silicon Laboratories Inc.

Inventor： Thomas Saroshan David ,  Aslam Rafi ,  Joshua Norem ,  Adrianus Josephus Bink ,  Daniel Cooley

IPC: G06F3/06

Abstract: An external nonvolatile memory device that includes a rewritable nonvolatile memory and a CMOS interface is disclosed. The interface includes a clock signal which is input to the external nonvolatile memory device. This clock signal is multiplied by an integer to create a memory serdes clock which is used to clock outgoing data. The memory serdes clock is also used to create a clock that is used to clock the incoming data from the main processing device. The external nonvolatile memory device also includes an encryption/decryption block that encrypts data read from the nonvolatile memory before it is transmitted over the interface, and decrypts data received from the interface before storing it in the nonvolatile memory. The encryption/decryption block may utilize a stream cipher.

公开(公告)号：US20240187402A1

公开(公告)日：2024-06-06

申请号：US18074744

申请日：2022-12-05

Applicant: Silicon Laboratories Inc.

Inventor： Heng Wee Cheng ,  Joshua Norem ,  Steven Cooreman ,  Phil Matthews

IPC: H04L9/40

CPC classification number: H04L63/083

Abstract: A system and method for performing execute-in-place is disclosed, wherein the code is encrypted using AES-GCM and stored in an external memory device. The system includes only one cipher function that is used to encrypt the three counter values that are used to decrypted the encrypted code and to validate the Message Authentication Code (MAC). In some embodiments, the system precalculates a hash subkey so that generation of the Counter 0 value can begin as soon as a valid memory address is available. In addition, the cipher function is modified to utilized two or more cipher generation circuits and only one key expansion circuit. This improves the speed of the operation without a complete duplication of the cipher function hardware. In another embodiment, the cipher function is unrolled so that two or more rounds of key expansion and cipher generation are performed each clock cycle.