公开(公告)号：US20230305983A1

公开(公告)日：2023-09-28

申请号：US17700907

申请日：2022-03-22

Applicant: Silicon Laboratories Inc.

Inventor： Aslam Rafi ,  Thomas Saroshan David ,  Daniel Cooley

IPC: G06F13/40 ,  G06F1/12

CPC classification number: G06F13/4068 ,  G06F1/12

Abstract: An interface between two devices is disclosed. To consume power, the signals used in the interface utilize CMOS signalling. Further, to achieve high speed, a reduced frequency clock is transmitted from one device to the second device. The second device has a clock multiplier to recreate the original clock. Both devices utilize a clock phase alignment block which aligns the phase of the clock with the incoming data. The clock phase alignment block utilizes a digital PLL to consume power. Further, since the digital PLL retains its state, the reduced frequency clock may be disabled when data is not being transmitted. This interface may be used to transmit serial data at rates up to and exceeding 2.5 Gbits/sec.

公开(公告)号：US20230305737A1

公开(公告)日：2023-09-28

申请号：US17700906

申请日：2022-03-22

Applicant: Silicon Laboratories Inc.

Inventor： Thomas Saroshan David ,  Aslam Rafi ,  Joshua Norem ,  Adrianus Josephus Bink ,  Daniel Cooley

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0613 ,  G06F3/0622 ,  G06F3/0679

Abstract: An external nonvolatile memory device that includes a rewritable nonvolatile memory and a CMOS interface is disclosed. The interface includes a clock signal which is input to the external nonvolatile memory device. This clock signal is multiplied by an integer to create a memory serdes clock which is used to clock outgoing data. The memory serdes clock is also used to create a clock that is used to clock the incoming data from the main processing device. The external nonvolatile memory device also includes an encryption/decryption block that encrypts data read from the nonvolatile memory before it is transmitted over the interface, and decrypts data received from the interface before storing it in the nonvolatile memory. The encryption/decryption block may utilize a stream cipher.

公开(公告)号：US12175118B2

公开(公告)日：2024-12-24

申请号：US17700906

申请日：2022-03-22

Applicant: Silicon Laboratories Inc.

Inventor： Thomas Saroshan David ,  Aslam Rafi ,  Joshua Norem ,  Adrianus Josephus Bink ,  Daniel Cooley

IPC: G06F3/06

Abstract: An external nonvolatile memory device that includes a rewritable nonvolatile memory and a CMOS interface is disclosed. The interface includes a clock signal which is input to the external nonvolatile memory device. This clock signal is multiplied by an integer to create a memory serdes clock which is used to clock outgoing data. The memory serdes clock is also used to create a clock that is used to clock the incoming data from the main processing device. The external nonvolatile memory device also includes an encryption/decryption block that encrypts data read from the nonvolatile memory before it is transmitted over the interface, and decrypts data received from the interface before storing it in the nonvolatile memory. The encryption/decryption block may utilize a stream cipher.

公开(公告)号：US11768794B1

公开(公告)日：2023-09-26

申请号：US17700907

申请日：2022-03-22

Applicant: Silicon Laboratories Inc.

Inventor： Aslam Rafi ,  Thomas Saroshan David ,  Daniel Cooley

IPC: G06F13/40 ,  G06F1/12

CPC classification number: G06F13/4068 ,  G06F1/12

Abstract: An interface between two devices is disclosed. To consume power, the signals used in the interface utilize CMOS signalling. Further, to achieve high speed, a reduced frequency clock is transmitted from one device to the second device. The second device has a clock multiplier to recreate the original clock. Both devices utilize a clock phase alignment block which aligns the phase of the clock with the incoming data. The clock phase alignment block utilizes a digital PLL to consume power. Further, since the digital PLL retains its state, the reduced frequency clock may be disabled when data is not being transmitted. This interface may be used to transmit serial data at rates up to and exceeding 2.5 Gbits/sec.