公开(公告)号：US20220277199A1

公开(公告)日：2022-09-01

申请号：US17750052

申请日：2022-05-20

Applicant: Huawei Technologies Co., Ltd. ,  TSINGHUA UNIVERSITY

Inventor： Bin GAO ,  Peng YAO ,  Kanwen WANG ,  Jianxing LIAO ,  Tieying WANG ,  Huaqiang WU

IPC: G06N3/08 ,  G06N3/04

Abstract: A method for data processing in a neural network system and a neural network system are provided. The method includes: inputting training data into a neural network system to obtain first output data, and adjusting, based on a deviation between the first output data and target output data, a weight value stored in at least one in-memory computing unit in some neural network arrays in a plurality of neural network arrays in the neural network system using parallel acceleration. The some neural network arrays are configured to implement computing of some neural network layers in the neural network system. The method may improve performance and recognition accuracy of the neural network system.

公开(公告)号：US20220275220A1

公开(公告)日：2022-09-01

申请号：US17747911

申请日：2022-05-18

Applicant: Tsinghua University ,  Tencent Technology (Shenzhen) Company Limited

Inventor： Jianshi TANG ,  Zhenxuan ZHAO ,  Yuan DAI ,  Zhengyou ZHANG ,  Jian YUAN ,  Huaqiang WU ,  He QIAN ,  Bin GAO

IPC: C09D5/24 ,  C09D7/61 ,  C09D7/20 ,  C09D175/04 ,  C09D163/00 ,  H01C10/10 ,  H01C17/00 ,  B25J9/16

Abstract: Embodiments of this application provide a method for preparing a thin film piezoresistive material, a thin film piezoresistive material, a robot, and a device. The method includes: determining a mass ratio of conductive particles to a cross-linked polymer in preparation of the thin film piezoresistive material, a value range of the mass ratio being 3:97 to 20:80; dispersing the conductive particles and the cross-linked polymer in a solvent according to the mass ratio, to obtain a first dispersion; and curing the first dispersion by using a liquid dropping method within a temperature range of 25° C. to 200° C., to obtain the thin film piezoresistive material. The technical solutions provided by the embodiments of this application provide a method for preparing a thin film piezoresistive material through liquid dropping, thereby effectively controlling the thickness of the piezoresistive material, so that the prepared thin film piezoresistive material has a relatively small thickness.

公开(公告)号：US20240320083A1

公开(公告)日：2024-09-26

申请号：US18574247

申请日：2021-12-13

Applicant: TSINGHUA UNIVERSITY

Inventor： Bin GAO ,  Peng YAO ,  Huaqiang WU ,  Jianshi TANG ,  He QIAN

IPC: G06F11/07

CPC classification number: G06F11/0793 ,  G06F11/073

Abstract: A storage and computation integrated apparatus and a calibration method therefor. The storage and computation integrated apparatus includes a first processing unit, which includes: a first computation memristor array; a first calibration memristor array; and a first processing unit. The calibration method includes: determining, by means of off-chip training, a first computation weight matrix which corresponds to a first computation memristor array, and writing the first computation weight matrix into the first computation memristor array; and on the basis of the first computation memristor array where the first computation weight matrix has been written and the first computation weight matrix, performing on-chip training on a first calibration memristor array, so as to adjust a weight value of the first calibration memristor array.

公开(公告)号：US20220374694A1

公开(公告)日：2022-11-24

申请号：US17882360

申请日：2022-08-05

Applicant: Huawei Technologies Co., Ltd. ,  Tsinghua University

Inventor： Bin GAO ,  Qi LIU ,  Leibin NI ,  Kanwen WANG ,  Huaqiang WU

IPC: G06N3/063

Abstract: A neural network circuit is described that includes a first sample-and-hold circuit, a reference voltage generation circuit, a first comparator circuit, and a first output circuit. The first sample-and-hold circuit generates a first analog voltage based on a first output current output by a first neural network computation array. The reference voltage generation circuit generates a reference voltage based on a first control signal. The first comparator circuit is connected to the first sample-and-hold circuit and the reference voltage generation circuit, and outputs a first level signal based on the first analog voltage and the reference voltage. The first output circuit samples the first level signal based on a second control signal, and outputs a first computation result that meets the first computation precision.

公开(公告)号：US20220374688A1

公开(公告)日：2022-11-24

申请号：US17049349

申请日：2020-03-06

Applicant: TSINGHUA UNIVERSITY

Inventor： Huaqiang WU ,  Peng YAO ,  Bin GAO ,  Qingtian ZHANG ,  He QIAN

IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08

Abstract: A training method and a training device for a neural network based on memristors are provided. The neural network includes a plurality of neuron layers connected one by one and weight parameters between the plurality of neuron layers, and the training method includes: training the weight parameters of the neural network, and programming a memristor array based on the weight parameters after being trained to write the weight parameters after being trained into the memristor array; and updating a critical layer or several critical layers of the weight parameters of the neural network by adjusting conductance values of at least part of memristors of the memristor array.

公开(公告)号：US20220076746A1

公开(公告)日：2022-03-10

申请号：US17530128

申请日：2021-11-18

Applicant: Huawei Technologies Co., Ltd. ,  TSINGHUA UNIVERSITY

Inventor： Bin GAO ,  Kanwen WANG ,  Junren CHEN ,  Rui ZHANG ,  Huaqiang WU

IPC: G11C13/00 ,  G06N3/063

Abstract: This application provides a storage device and a data writing method. The storage device may be used in a neural network. The storage device includes a memristor unit, a current-controlled circuit, and a write circuit. The memristor unit has a structure of one-transistor and one-resistive random access memory 1T1R. The current-controlled circuit is configured to limit a current passing through the memristor unit to a target current, where the target current is determined based on target conductance of the memristor unit and a gate voltage of the transistor, and the target conductance is used to indicate target data to be written into the memristor unit. The write circuit is configured to load a write voltage to the memristor unit in cooperation with the current-controlled circuit, to write the target data to the memristor unit.

公开(公告)号：US20220061729A1

公开(公告)日：2022-03-03

申请号：US17412016

申请日：2021-08-25

Applicant: TSINGHUA UNIVERSITY

Inventor： Huaqiang WU ,  Zhengwu LIU ,  Jianshi TANG ,  Bin GAO ,  He QIAN

IPC: A61B5/304 ,  G11C13/00 ,  A61B5/31 ,  A61B5/00

Abstract: A signal processing apparatus and a signal processing method are provided. The signal processing apparatus includes a memristor array, an input circuit, a first switching circuit, a second switching circuit, an output circuit, and a control circuit. The memristor array includes memristor units and is connected to source lines, word lines and bit lines. The control circuit is configured to control the first switching circuit to select at least one source line to apply at least one first signal to the at least one source line respectively, control the second switching circuit to select and activate at least one word line to apply the at least one first signal to a memristor unit corresponding to the at least one word line, and control the output circuit to output a plurality of second signals based on conductivity values of memristors of the memristor array.

公开(公告)号：US20210184025A1

公开(公告)日：2021-06-17

申请号：US17058211

申请日：2018-08-03

Applicant: TSINGHUA UNIVERSITY

Inventor： Feng XU ,  Bin GAO ,  Xinyi LI ,  Huaqiang WU ,  He QIAN

IPC: H01L29/775 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165

Abstract: A nanowire transistor and a manufacture method thereof are provided. The nanowire transistor includes a semiconductor wire, a semiconductor layer, a source electrode and a drain electrode. The semiconductor wire includes a first semiconductor material and includes a source region, a drain region, and a channel region, along an axial direction of the semiconductor wire, the channel region is between the source region and the drain region; the semiconductor layer includes a second semiconductor material and covers the channel region of the semiconductor wire; the source electrode is in the source region of the semiconductor wire and is in direct contact with the source region of the semiconductor wire, and the drain electrode is in the drain region of the semiconductor wire and is in direct contact with the drain region of the semiconductor wire.