Abstract:
This application provides a storage device and a data writing method. The storage device may be used in a neural network. The storage device includes a memristor unit, a current-controlled circuit, and a write circuit. The memristor unit has a structure of one-transistor and one-resistive random access memory 1T1R. The current-controlled circuit is configured to limit a current passing through the memristor unit to a target current, where the target current is determined based on target conductance of the memristor unit and a gate voltage of the transistor, and the target conductance is used to indicate target data to be written into the memristor unit. The write circuit is configured to load a write voltage to the memristor unit in cooperation with the current-controlled circuit, to write the target data to the memristor unit.
Abstract:
A signal processing apparatus and a signal processing method are provided. The signal processing apparatus includes a memristor array, an input circuit, a first switching circuit, a second switching circuit, an output circuit, and a control circuit. The memristor array includes memristor units and is connected to source lines, word lines and bit lines. The control circuit is configured to control the first switching circuit to select at least one source line to apply at least one first signal to the at least one source line respectively, control the second switching circuit to select and activate at least one word line to apply the at least one first signal to a memristor unit corresponding to the at least one word line, and control the output circuit to output a plurality of second signals based on conductivity values of memristors of the memristor array.
Abstract:
A nanowire transistor and a manufacture method thereof are provided. The nanowire transistor includes a semiconductor wire, a semiconductor layer, a source electrode and a drain electrode. The semiconductor wire includes a first semiconductor material and includes a source region, a drain region, and a channel region, along an axial direction of the semiconductor wire, the channel region is between the source region and the drain region; the semiconductor layer includes a second semiconductor material and covers the channel region of the semiconductor wire; the source electrode is in the source region of the semiconductor wire and is in direct contact with the source region of the semiconductor wire, and the drain electrode is in the drain region of the semiconductor wire and is in direct contact with the drain region of the semiconductor wire.
Abstract:
A computing apparatus and a robustness processing method thereof. The robustness processing method includes: based on model parameters of a target algorithm model, obtaining a mapping relationship between the model parameters and the first computing memristor array; based on an influence factor that determines a critical weight device, determining a way to obtain a weight criticality of the plurality of memristor devices from the influence factor; obtaining an input set of the algorithm model, and determining a criticality value for each of the plurality of memristor devices according to the way; determining a critical weight device among the plurality of memristor devices according to the criticality value for each of the plurality of memristor devices; and based on the critical weight device, performing an optimization processing on the first processing unit.
Abstract:
Disclosed are a quantization method and quantization apparatus for a weight of a neural network, and a storage medium. The neural network is implemented on the basis of a crossbar-enabled analog computing-in-memory (CACIM) system, and the quantization method includes: acquiring a distribution characteristic of a weight; and determining, according to the distribution characteristic of the weight, an initial quantization parameter for quantizing the weight to reduce a quantization error in quantizing the weight. The quantization method provided by the embodiments of the present disclosure does not pre-define the quantization method used, but determines the quantization parameter used for quantizing the weight according to the distribution characteristic of the weight to reduce the quantization error, so that the effect of the neural network model is better under the same mapping overhead, and the mapping overhead is smaller under the same effect of the neural network model.
Abstract:
This application discloses a conductive paste, a preparation method thereof, and a preparation method of a conductive film using the conductive paste. The conductive paste comprises: a thermoplastic polyurethane, conductive particles, and an organic solvent, the thermoplastic polyurethane and the conductive particles being proportionally mixed in the organic solvent, and the thermoplastic polyurethane being dispersed in the form of particles among the conductive particles. A thermoplastic polyurethane elastomer is used as a binder, and the conductive particles are mixed in the organic solvent containing the thermoplastic polyurethane elastomer. The conductive particles ensure the conductivity of the conductive film prepared using the conductive paste. The thermoplastic polyurethane has strong adhesion ability, and is suitable for use on the surface of most substrates, to form a conductive film with good adhesion and no cracking.
Abstract:
A compilation method, a compilation apparatus suitable for an In-Memory Computing apparatus, a computing device and a storage medium. The compilation method includes: acquiring calculation information of an algorithm to be compiled; converting the algorithm to be compiled into the first intermediate representation according to the calculation information; mapping the first intermediate representation to the second intermediate representation; and compiling the algorithm to be compiled into instruction information recognized by the In-Memory Computing apparatus according to the hardware information, to make the In-Memory Computing apparatus execute the instruction information. The compilation method may compile the calculation information into instructions that may be directly executed by the In-Memory Computing apparatus, so as to realize the effect of accelerating the operations of various algorithms by using the In-Memory Computing apparatus.
Abstract:
Disclosed are a video stitching method and a video stitching device. The video stitching method is applicable for stitching a first video and a second video, and includes: performing feature extraction, feature matching and screening on a first target frame of the first video and a second target frame of the second video, so as to obtain a first feature point pair set; performing forward tracking on the first target frame and the second target frame, so as to obtain a second feature point pair set; performing backward tracking on the first target frame and the second target frame, so as to obtain a third feature point pair set; and calculating a geometric transformation relationship between the first target frame and the second target frame according to a union of the first feature point pair set, the second feature point pair set and the third feature point pair set.
Abstract:
An Al-W-O stack structure applicable to a resistive random access memory according to an embodiment of the invention comprises a tungsten top electrode, a tungsten oxide layer formed on the tungsten lower electrode, an aluminum oxide layer formed on the tungsten oxide layer and an aluminum top electrode formed on the aluminum oxide layer. The invention utilizes the different properties of two metals, namely aluminum and tungsten in bonding with oxygen ions, to obtain a resistive random access memory with more stable performances, lower power consumption and larger high resistance-low resistance ratio.
Abstract:
At least one embodiment of the present disclosure provides a data processing method based on a memristor array and an electronic apparatus. The data processing method includes: acquiring a plurality of first analog signals; setting the memristor array, and writing data of a parameter matrix corresponding to the data processing into the memristor array; and inputting the plurality of first analog signals into a plurality of column signal input terminals of the set memristor array, respectively, controlling operation of the memristor array to perform the data processing on the plurality of first analog signals, and obtaining a plurality of second analog signals after performing the data processing at a plurality of row signal output terminals of the memristor array, respectively.