公开(公告)号：FR2769754A1

公开(公告)日：1999-04-16

申请号：FR9712890

申请日：1997-10-15

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SUN SHIH WEI ,  YEW TRI RUNG

IPC: H01L21/8242

Abstract: An IC component, with an embedded memory and logic circuits on a single substrate, is produced by forming a contact opening in a conformal protective layer (129), which covers transmission and logic FETs (104, 120), to expose a source or drain region (118) of one of the transmission FETs (104), forming a charge storage capacitor (130, 132, 134) connected to this source or drain region (118) and then removing the protective layer (129) at least from the logic circuit regions. Production of an integrated circuit component, which includes an embedded memory and logic circuits on a single substrate, comprises: (i) forming a substrate (100) with transmission FETs (104) in and on embedded DRAM regions and with logic FETs (120) in and on logic circuit regions; (ii) forming a conformal protective layer (129) over the FETs (104, 120), the layer having the same thickness over the gate electrodes and the source/drain regions (128) of the logic FETs (120); (iii) removing a portion of the protective layer (129) to form a contact opening which exposes a source or drain region (118) of one of the transmission FETs (104); (iv) forming a lower capacitor electrode (130) in contact with the source/drain region (118) of the transmission FET (104); (v) successively forming a capacitor dielectric layer (132) and an upper capacitor electrode (134) above the lower capacitor electrode (130) to form a charge storage capacitor for the transmission FET (104); and (vi) removing the protective layer (129) at least from the logic circuit regions. An Independent claim is also included for production of a similar integrated circuit component, in which the embedded memory is an embedded DRAM.

公开(公告)号：FR2765397A1

公开(公告)日：1998-12-31

申请号：FR9800712

申请日：1998-01-23

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YEW TRI RUNG ,  LUR WATER ,  SUN SHIH WEI

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/8242

Abstract: A method of fabricating a DRAM device to reduce the stress and enhance the adhesion between the top electrode and the interlevel dielectric layer, includes forming a titanium layer between the top electrode and the interlevel dielectric layer. A titanium oxide layer and a titanium silicide are formed between the titanium layer and the interlevel dielectric layer in post thermal procedures, which enhances the adhesion and avoids cracks and leakage current between the top electrode and the interlevel dielectric layer.

公开(公告)号：FR2760129A1

公开(公告)日：1998-08-28

申请号：FR9705290

申请日：1997-04-29

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SUN SHIH WEI

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/28

Abstract: A method of manufacturing interconnect in semiconductor device comprises of the steps: (1) on one semiconductor substrate, adjacent to one first insulator supplying one conductive layer, in which the conductive layer has top surface sharing common plane with first insulator; (2) on conductive layer and top surface of first insulator depositing one etch stop layer, which is different from first insulator; (3) on etch stop layer depositing one second insulator, which is different from etch stop layer; (4) etching one via to expose part of etch stop layer, and etched via at least locally formed on conductive layer; (5) removing etch stop layer in via; (6) in via filling one conductive material.

公开(公告)号：FR2763424B1

公开(公告)日：2003-06-27

申请号：FR9705992

申请日：1997-05-15

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YEW TRI RUNG ,  LIU MONG CHUNG ,  LUR WATER ,  SUN SHIH WEI

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522

公开(公告)号：FR2772986B1

公开(公告)日：2000-02-11

申请号：FR9716332

申请日：1997-12-23

Applicant: UNITED MICROELECTRONICS CORP

Inventor： YANG MING SHENG ,  WU JUAN YUAN ,  LUR WATER ,  SUN SHIH WEI

IPC: H01L21/304 ,  C09K3/14 ,  H01L21/321 ,  H01L21/302 ,  H01L21/461

Abstract: A method for chemical mechanical polishing a component includes providing an oxide layer and forming at least one via through the oxide layer. A tungsten layer is formed within the via and over the oxide layer. A first chemical mechanical polishing step is carried out on a polishing pad using a first slurry having an oxidizing component and having a pH of approximately 2 to approximately 4 to remove the tungsten layer from over the oxide layer. A second chemical mechanical polishing step is carried out on the polishing pad using a second slurry having a pH of approximately 2 to approximately 4 to polish scratches out of the oxide layer.

公开(公告)号：FR2763174B1

公开(公告)日：1999-12-31

申请号：FR9705665

申请日：1997-05-07

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SUN SHIH WEI ,  YEW TRI RUNG

IPC: H01L21/3205 ,  H01L21/306 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78

Abstract: A method of forming a DRAM includes forming a transfer FET on a substrate, the FET having a gate on a gate oxide layer above the substrate and a first and second source/drain region in the substrate on either side of a channel region under the gate. The first and second source/drain regions are typically exposed or nearly exposed in a spacer etch process. A silicon nitride etch stop layer is deposited over the entire structure and then a thick layer of oxide is deposited on the device. Chemical mechanical polishing is performed to provide a planar surface on the thick oxide layer. An opening is formed through the thick layer of oxide above the first source/drain region, stopping at the etch stop layer. The etch stop layer is removed within the opening in the thick layer of oxide and the underlying thin oxide layer is etched. A capacitor electrode can then be formed in contact with the exposed portion of the first source/drain region. A similar self-aligned method can be used to form the bit line contact for the device using the etch stop layer as a stop for the bit line contact etch. Practice of the method provides a manufacturing method having improved reliability and ease of use, particularly when practiced for DRAM capacitors that incorporate high dielectric constant dielectrics. The materials preferred for use within such DRAM capacitors have smaller process margins and so particularly benefit from the improved structure and process.

公开(公告)号：FR2763743B1

公开(公告)日：1999-07-23

申请号：FR9711068

申请日：1997-09-05

Applicant: UNITED MICROELECTRONICS CORP

Inventor： LIN TONY ,  LUR WATER ,  SUN SHIH WEI

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/78

Abstract: A method of making a self-aligned silicide which has an impurity diffusion region in a lower part of the source/drain regions adjacent to the isolating region. The method includes performing an ion implantation operation at a large tilt angle, which increases the junction depth of the source/drain regions and prevents the metallic silicide lying at the edge of the isolating region from getting too close to the source/drain junction and causing unwanted current leakages. The isolating regions are overetched, which exposes the surface of the source/drain regions. The metal silicide layer can thus be formed over the exposed source/drain surfaces, resulting in more surface area for the formation of a wide border contact window, resulting in a lowering of both contact resistance and sheet resistance there.

公开(公告)号：FR2770028A1

公开(公告)日：1999-04-23

申请号：FR9713228

申请日：1997-10-22

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SUN SHIH WEI

IPC: H01L21/768 ,  H01L23/522

Abstract: A multilevel interconnect is formed which uses air (74) as a dielectric between wiring lines (66) bounded on an upper surface by a capping layer (70). A sacrificial layer is used to separate the wiring lines and is consumed leaving air gaps. A multilevel interconnect is formed which uses air as a dielectric between wiring lines. A pattern of wiring lines is formed over an insulating layer (62), a first wiring line is laterally separated from a second wiring line by a sacrificial layer. The surface of this layer is recessed below the surfaces of the wiring lines. A capping layer (70) is formed over the recessed surface and the wiring lines. The sacrificial layer is consumed through the capping layer leaving an air dielectric (74) between the two wiring lines bounded on an upper surface by the capping layer.

公开(公告)号：FR2767965A1

公开(公告)日：1999-03-05

申请号：FR9710703

申请日：1997-08-27

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SUN SHIH WEI ,  TSAI MENG JIN

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/316 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/336

Abstract: Production if an IC device requires the following steps to be performed - Provide semiconductor substrate with surface and that substrate has a 1st area, which will generate 1st MOS devices and a 2nd area which will generate several 2nd MOS devices; - Provide 1st dopant of 1st density on 1st area surface of substrate; - Provide 2nd dopant of 2nd density on 2nd area surface of substrate; - Oxidation substrate surface in single oxidation process, and generate oxide with 1st thickness on 1st area, and generate oxide with 2nd different thickness on 2nd area of substrate; - Generate 1st MOS device with 1st thickness oxide on 1st area, and generate 2nd MOS device with 2nd thickness oxide on 2nd area of substrate.

公开(公告)号：FR2766293A1

公开(公告)日：1999-01-22

申请号：FR9716074

申请日：1997-12-18

Applicant: UNITED MICROELECTRONICS CORP

Inventor： WU H J ,  SUN SHIH WEI ,  CHEN JACOB ,  YEW TRI RUNG

IPC: H01L21/8242 ,  H01L27/108