公开(公告)号：US20210296291A1

公开(公告)日：2021-09-23

申请号：US16846429

申请日：2020-04-13

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Chi-Hai Kuo ,  Kai-Ming Yang ,  Cheng-Ta Ko

IPC: H01L25/075 ,  H01L33/62 ,  H01L33/52 ,  H01L33/00

Abstract: A manufacturing method of chip package structure includes following steps. A carrier is provided. A first patterned circuit layer and a first dielectric layer covering the first patterned circuit layer have been formed on the carrier. A flat structure layer is formed on the first dielectric layer. A second dielectric layer is formed on the first dielectric layer and covers the flat structure layer and a portion of the first dielectric layer. A second patterned circuit layer is formed on the second dielectric layer. The second patterned circuit layer includes a plurality of pads. An orthographic projection of the flat structure layer on the carrier overlaps orthographic projections of the pads on the carrier. A plurality of chips are disposed on the pads. A molding compound is formed to cover the second dielectric layer and encapsulate the chips and the pads.

公开(公告)号：US20210118839A1

公开(公告)日：2021-04-22

申请号：US16687557

申请日：2019-11-18

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Cheng-Ta Ko ,  Ra-Min Tain ,  Tzyy-Jang Tseng

IPC: H01L23/00 ,  H01L23/538

Abstract: A chip package structure includes a substrate, at least two chips, a plurality of first pads, a plurality of first micro bumps, and a bridging element. The substrate has a first surface and a second surface opposite to the first surface. The two chips are disposed on the first surface of the substrate and are horizontally adjacent to each other. Each chip has an active surface. The first pads are disposed on the active surface of each of the chips. The first micro bumps are disposed on the first pads and have the same size. The bridging element is disposed on the first micro bumps such that one of the chips is electrically connected to another of the chips through the first pads, the first micro bumps, and the bridging element.

公开(公告)号：US10957658B2

公开(公告)日：2021-03-23

申请号：US16866530

申请日：2020-05-04

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Cheng-Ta Ko ,  Yu-Hua Chen ,  Tzyy-Jang Tseng ,  Ra-Min Tain

IPC: H01L23/16 ,  H01L23/66 ,  H01L23/00 ,  H01L23/31

Abstract: A package structure includes a redistribution structure, a chip, one or more structural reinforcing elements, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The one or more structural reinforcing elements are disposed over the redistribution structure. The structural reinforcing element has a Young's modulus in a range of 30 to 200 GPa. The protective layer overlays the chip and a sidewall of the structural reinforcing element.

公开(公告)号：US10950535B2

公开(公告)日：2021-03-16

申请号：US16785630

申请日：2020-02-09

Applicant: Unimicron Technology Corp.

Inventor： Chun-Min Wang ,  Pu-Ju Lin ,  Cheng-Ta Ko

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00

Abstract: A package structure includes a redistribution structure, a chip, an inner conductive reinforcing element, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The inner conductive reinforcing element is disposed over the redistribution structure. The inner conductive reinforcing element has a Young's modulus in a range of from 30 to 200 GPa. The protective layer covers the chip and a sidewall of an opening of the inner conductive reinforcing element.

公开(公告)号：US10658282B2

公开(公告)日：2020-05-19

申请号：US16167540

申请日：2018-10-23

Applicant: Unimicron Technology Corp.

Inventor： Cheng-Ta Ko ,  Kai-Ming Yang ,  Yu-Hua Chen ,  Tzyy-Jang Tseng

IPC: H01L23/498

Abstract: A package substrate structure includes a first substrate, a second substrate, a plurality of conductive pillars and an adhesive layer. The first substrate includes a plurality of vias and a plurality of pads. The vias and the pads are disposed on the first substrate, and fills the vias. The second substrate is disposed opposite to the first substrate. Each conductive pillar is disposed between the first substrate and the second substrate, where each conductive pillar electrically connects each pad and the second substrate, and the adhesive layer fills the gaps between the conductive pillars. A bonding method of the package substrate structure is also provided.

公开(公告)号：US11991824B2

公开(公告)日：2024-05-21

申请号：US17448893

申请日：2021-09-26

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Chi-Hai Kuo ,  Shao-Chien Lee ,  Ming-Ru Chen ,  Cheng-Chung Lo

IPC: H05K1/02 ,  G02F1/1333 ,  G02F1/1368 ,  H05K1/03 ,  H05K1/11 ,  H05K3/00 ,  H10K59/12 ,  H10K59/123 ,  H10K59/124 ,  H10K59/131

CPC classification number: H05K1/115 ,  H05K1/0306 ,  H05K3/0067 ,  H05K3/0094

Abstract: A circuit board structure includes a first sub-circuit board, a second sub-circuit board, and a third sub-circuit board. The first sub-circuit board has an upper surface and a lower surface opposite to each other, and includes at least one first conductive through hole. The second sub-circuit board is disposed on the upper surface of the first sub-circuit board and includes at least one second conductive through hole. The third sub-circuit board is disposed on the lower surface of the first sub-circuit board and includes at least one third conductive through hole. At least two of the first conductive through hole, the second conductive through hole, and the third conductive through hole are alternately arranged in an axial direction perpendicular to an extending direction of the first sub-circuit board. The first, second and third sub-circuit boards are electrically connected to one another.

公开(公告)号：US11955587B2

公开(公告)日：2024-04-09

申请号：US17227391

申请日：2021-04-12

Applicant: Unimicron Technology Corp.

Inventor： Jeng-Ting Li ,  Chi-Hai Kuo ,  Cheng-Ta Ko ,  Pu-Ju Lin

IPC: H01L33/62 ,  H01L27/15 ,  H01L33/00

CPC classification number: H01L33/62 ,  H01L27/156 ,  H01L33/005 ,  H01L2933/0066

Abstract: A light emitting diode (LED) package structure includes a glass substrate, conductive through holes, active elements, an insulating layer, LEDs and pads. The glass substrate has an upper surface and a lower surface. The conductive through holes penetrate the glass substrate and connect the upper and the lower surfaces. The active elements are disposed on the upper surface of the glass substrate and electrically connected to the conductive through holes. The insulating layer is disposed on the upper surface and covers the active elements. The LEDs are disposed on the insulating layer and electrically connected to at least one of the active elements. The pads are disposed on the lower surface of the glass substrate and electrically connected to the conductive through holes. A source of at least one active elements is directly electrically connected to at least one of the corresponding pads through the corresponding conductive through hole.

公开(公告)号：US20230164928A1

公开(公告)日：2023-05-25

申请号：US17945106

申请日：2022-09-15

Applicant: Unimicron Technology Corp.

Inventor： Cheng-Ta Ko ,  Pu-Ju Lin ,  Shih-Chieh Chen ,  Chi-Hai Kuo ,  Jeng-Ting Li

IPC: H05K3/46 ,  H05K1/03 ,  H05K1/11 ,  H05K3/06

CPC classification number: H05K3/4691 ,  H05K1/0393 ,  H05K1/118 ,  H05K3/06 ,  H05K2201/0154 ,  H05K2201/09509

Abstract: A flexible circuit board and a manufacturing method thereof are provided. The flexible circuit board includes a circuit structure, a first cover layer, and a second cover layer. The circuit structure has a top surface and a bottom surface opposite to the top surface. The circuit structure includes multiple circuit layers and multiple insulating layers stacked alternately. A material of the insulating layers is a photosensitive dielectric material and a Young's modulus of the insulating layers is between 0.36 GPa and 8 GPa. The first cover layer is disposed on the top surface of the circuit structure. The second cover layer is disposed on the bottom surface of the circuit structure.

公开(公告)号：US20230163074A1

公开(公告)日：2023-05-25

申请号：US17569509

申请日：2022-01-06

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  John Hon-Shing Lau ,  Pu-Ju Lin ,  Cheng-Ta Ko

IPC: H01L23/532 ,  H01L23/495 ,  H01L23/538

CPC classification number: H01L23/5329 ,  H01L23/53238 ,  H01L23/49503 ,  H01L23/5389

Abstract: A chip packaging structure and a manufacturing method thereof are provided. The chip packaging structure includes a substrate, at least one first chip, an adhesive material, a redistribution circuit structure, and multiple second chips. The substrate has a first surface, a second surface opposite to the first surface, and at least one cavity. The at least one first chip is disposed in the at least one cavity. The adhesive material is disposed in the at least one cavity and located between the substrate and the at least one first chip. The redistribution circuit structure is disposed on the first surface of the substrate, and is electrically connected to the at least one first chip. The second chips are disposed on the redistribution circuit structure, and are electrically connected to the redistribution circuit structure.

公开(公告)号：US11637047B2

公开(公告)日：2023-04-25

申请号：US17875443

申请日：2022-07-28

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Kai-Ming Yang ,  Cheng-Ta Ko

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L21/78

Abstract: A manufacturing method of a chip package structure includes the following steps. A plurality of chips is disposed on a first insulating layer. The back surface of each of the chips is in direct contact with the first insulating layer. A stress buffer layer is formed to extend and cover the active surface and the peripheral surface of each of the chips, and a bottom surface of the stress buffer layer is aligned with the back surface of each of the chips. The stress buffer layer has an opening exposing a part of the active surface of each of the chips, and the redistribution layer is electrically connected to each of the chips through the opening. A plurality of solder balls is electrically connected to the redistribution layer exposed by the blind holes. A singularizing process is performed to form a plurality of chip package structures separated from each other.