公开(公告)号：EP1310955A3

公开(公告)日：2007-02-21

申请号：EP02257758.9

申请日：2002-11-08

Applicant: STMicroelectronics, Inc.

Inventor： Venca, Alessandro ,  Posat, Baris ,  Ozanoglu, Kemal ,  Alini, Roberto

IPC: G11B19/02 ,  G11B5/012 ,  G11B5/02

CPC classification number: G11B5/022 ,  G11B5/012 ,  G11B5/02 ,  G11B5/09 ,  G11B2005/0013

Abstract: A circuit and method are disclosed for relatively rapidly causing the current flowing through a write head to transition between steady states without generating an appreciable amount of capacitively-coupled noise. Embodiments of the present invention generally provide drive voltage signals to the write head that have no common mode voltage levels during transitions between steady state current levels in the write head. In other words, the drive voltage signals applied to the write head are substantially entirely differential during write head current transitions. In an exemplary embodiment of the present invention, a driver circuit (100) includes switching circuitry (111,112,113,114,116,117,118,119) connected between the terminals (42A,42B) of the write head (42) and reference voltage supplies, such as positive and negative voltage supplies. The driver circuit further includes timing circuitry (125) that generates control signals for controlling the switching circuitry.

公开(公告)号：EP1162469B1

公开(公告)日：2007-01-31

申请号：EP01304419.3

申请日：2001-05-18

Applicant: STMicroelectronics, Inc.

Inventor： Gupta, Vidyabhusan

IPC: G01R15/20 ,  G01R31/3173 ,  G01R31/3161

CPC classification number: G01R31/3004

公开(公告)号：EP0964445B1

公开(公告)日：2007-01-03

申请号：EP99304395.9

申请日：1999-06-04

Applicant: STMicroelectronics, Inc.

Inventor： Chiu, Anthony

IPC: H01L21/56 ,  H01L21/60 ,  H01L23/485 ,  H01L29/06

CPC classification number: H01L21/563 ,  H01L24/28 ,  H01L29/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07811 ,  H01L2924/10157 ,  H01L2924/10158 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/18301 ,  H01L2924/30107 ,  H01L2924/3511 ,  H01L2924/00

公开(公告)号：EP1736993A1

公开(公告)日：2006-12-27

申请号：EP06252950.8

申请日：2006-06-07

Applicant: STMicroelectronics, Inc.

Inventor： Dray, Cyrille ,  Barasinski, Sebastien ,  Lasseuguette, Jean ,  Frey, Christophe ,  Fournel, Richard

IPC: G11C11/16 ,  G11C7/18 ,  G11C8/14

CPC classification number: G11C7/18 ,  G11C7/12 ,  G11C11/15 ,  G11C11/16

Abstract: A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row. A second write signal is applied to one bit line to actuate the second selection circuit/transistor for the column corresponding to that one bit line and cause a write current to flow through the second source-drain path of the actuated second selection circuit/transistor and the corresponding write bit line to write data into at least one memory element in that column.

Abstract translation: 随机存取存储器阵列包括排列成行和列的随机存取存储器元件。 每行的元素具有字线和写数字线，并且每列的元素具有位线和写位线。 用于每行的第一选择电路/晶体管具有耦合在写入数字线中的第一源极 - 漏极通路和耦合到字线的栅极端子。 用于每列的第二选择电路/晶体管具有在写位线中耦合的第二源极 - 漏极路径和耦合到位线的栅极端子。 第一写入信号被施加到一个字线以对与该一条字线相对应的行进行第一选择电路/晶体管的驱动，并且使得写入电流流过被驱动的第一选择电路/晶体管的第一源极 - 漏极通路，并且 相应的写数字行将数据写入该行中的某些存储器元素。 第二写入信号被施加到一个位线以启动与该一个位线对应的列的第二选择电路/晶体管，并且使得写入电流流过被致动的第二选择电路/晶体管的第二源极 - 漏极通路，并且 相应的写位线将数据写入该列中的至少一个存储器元件。

公开(公告)号：EP1729468A2

公开(公告)日：2006-12-06

申请号：EP06252724.7

申请日：2006-05-25

Applicant: STMicroelectronics, Inc.

Inventor： Langevin, Michael ,  Pilkington, Charles

IPC: H04L12/56

CPC classification number: H04L49/15 ,  H04L49/205 ,  H04L49/506

Abstract: A network-on-chip interconnects an array of integrated circuit resources. The network-on-chip includes at least one vertical communications ring per column of the array and at least one horizontal communications ring per row of the array. A network interface is associated:with each resource of the array and operates to interface the communications rings with each other and the resource with the communications rings. A ring hop is provided at each network interface and for each communications ring thereat. Each ring hop functions as an add/drop multiplexer with respect to inserting packets onto the associated communications ring and extracting packets from the associated communications ring. Packets are communicated over the vertical/horizontal rings using a logical transport channel that flows in a cyclic manner through the communications ring without interruption. A back pressure mechanism allows the ring hops on a given communications ring to address overflow conditions on that ring, and a request mechanism allows the ring hops on a given communications ring to request use of that ring to carry a packet communication.

Abstract translation: 片上网络互连集成电路资源阵列。 片上网络包括阵列每列中的至少一个垂直通信环和阵列每行中的至少一个水平通信环。 网络接口相关联：与阵列的每个资源并且操作以将通信环彼此和资源与通信环相连接。 在每个网络接口和每个通信环上提供环形跳。 每个环回作为关于在相关联的通信环上插入分组并从相关联的通信环提取分组的分插复用器。 数据包通过垂直/水平环通过通信环路循环流动而不中断的逻辑传输信道进行通信。 背压机制允许给定通信环上的环形跳，以解决该环上的溢出情况，并且请求机制允许给定通信环上的环跳，以请求使用该环来携带分组通信。

公开(公告)号：EP1271480A3

公开(公告)日：2006-12-06

申请号：EP02253885.4

申请日：2002-05-31

Applicant: STMicroelectronics, Inc.

Inventor： Heydari, Fereidoon ,  Ozdemir, Hakan

IPC: G11B5/596

CPC classification number: G11B5/59655 ,  G11B5/59688

Abstract: A new technique for Hard Disk Drive (HDD) servo-burst demodulation is provided. A 4-samples per dibit Discrete Fourier Transform (DFT) amplitude estimation is used to calculate the read-head servo-position error signal. Comparatively, the conventional method of burst demodulation ― called burst integration ― typically uses more than 8 samples/dibit. Consequently, the new 4-samples/dibit DFT burst-demodulation scheme requires fewer samples per dibit than does burst integration, thus reducing the disk space occupied by the burst data while increasing the performance as compared to burst integration. Furthermore, the DFT scheme does not require the samples to be synchronized to any particular points of the servo burst, and can include an averaging algorithm that further improves performance for a given Signal to Noise Ratio (SNR). Moreover, the same sample-clocking circuit that detects the Gray Code servo information can also implement the DFT burst-demodulation scheme to demodulate the servo burst.

公开(公告)号：EP1727150A2

公开(公告)日：2006-11-29

申请号：EP06251760.2

申请日：2006-03-30

Applicant: STMicroelectronics, Inc.

Inventor： Lysinger, Mark

IPC: G11C15/00 ,  G11C15/04

CPC classification number: G06F7/74 ,  G11C15/00 ,  G11C15/04

Abstract: A priority encoder can be used for a Content-Addressable Memory (CAM) device that typically has an array of CAM cells arranged in columns and rows with each row having a match signal indicative that compare data has matched data within the respective row. A priority encoder is operatively connected to the array of CAM cells and determines a highest priority matching address for data within the array of CAM cells. The priority encoder includes match lines associated with respective rows and precharged bus lines connected into respective match lines that are discharged whenever there is a match signal such that the highest precharged bus line discharged results in an encoded address.

Abstract translation: 优先编码器可以用于通常具有排列成列和行的CAM单元阵列的内容寻址存储器（CAM）设备，每个行具有指示比较数据具有相应行内的匹配数据的匹配信号。 优先编码器可操作地连接到CAM单元阵列，并确定CAM单元阵列内的数据的最高优先级匹配地址。 优先编码器包括与相应行相关联的匹配线和连接到相应匹配线中的预充电总线，每当匹配信号被放电时，放电的最高预充电总线导致编码地址。

公开(公告)号：EP1317713B1

公开(公告)日：2006-11-02

申请号：EP01968767.2

申请日：2001-09-10

Applicant: STMicroelectronics, Inc. ,  Axalto S.A. ,  Schlumberger Technologies Operating Ltd.

Inventor： LEAMING, Taylor, J. ,  LEYDIER, Robert, Antoine

IPC: G06F13/38

CPC classification number: G06K19/07733 ,  G06F13/385 ,  G06K19/07

Abstract: A method and device are disclosed for detecting successful transfers between a Universal Serial Bus (USB) port and a USB smart card and generating a signal that provides an indication of the USB transaction activity. This USB transaction activity signal is modulated according to the USB transaction activity and drives a Light Emitting Diode (LED) in a preferred embodiment of the invention. A counter internal to the USB smart card scales the transaction activity signal such that it is perceptible to the user. Because the current through the LED depends upon the USB transaction activity, the brightness of the LED varies according to the USB transaction activity. The LED may be driven from a current mirror sink or source, or a current switch sink or source.

公开(公告)号：EP1715696A2

公开(公告)日：2006-10-25

申请号：EP06076530.2

申请日：1999-12-07

Applicant: STMicroelectronics, Inc.

Inventor： Owen, Jefferson Eugene ,  McDade, Darryn

IPC: H04N7/50 ,  H04N7/26

Abstract: A digital video decoder comprising a bit unpacker that utilizes at least an encoded video data stream to produce a prediction data stream and a coding data stream; a motion compensation instruction encoder communicably coupled to the bit unpacker, the motion compensation instruction encoder utilizing at least the prediction data stream to selectively produce a set of motion compensation instructions; and a block decoder communicably coupled to the bit unpacker, the block decoder utilizing at least the coding data stream to produce a set of error terms.

Abstract translation: 一种数字视频解码器，包括利用至少编码视频数据流产生预测数据流和编码数据流的比特解包器; 运动补偿指令编码器，其可通信地耦合到所述位解码器，所述运动补偿指令编码器至少利用所述预测数据流选择性地产生一组运动补偿指令; 以及块解码器，其可通信地耦合到所述位解包器，所述块解码器至少利用所述编码数据流来产生一组误差项。

公开(公告)号：EP1710693A2

公开(公告)日：2006-10-11

申请号：EP06251747.9

申请日：2006-03-30

Applicant: STMicroelectronics, Inc.

Inventor： Colavin, Osvaldo M. ,  Rizzo, Davide

IPC: G06F9/38

CPC classification number: G06F9/383

Abstract: A processor executes one or more prefetch threads and one or more main computing threads. Each prefetch thread executes instructions ahead of a main computing thread to retrieve data for the main computing thread, such as data that the main computing thread may use in the immediate future. Data is retrieved for the prefetch thread and stored in a memory, such as data fetched from an external memory and stored in a buffer. A prefetch controller determines whether the memory is full. If the memory is full, a cache controller stalls at least one prefetch thread. The stall may continue until at least some of the data is.transferred from the memory to a cache for use by at least one main computing thread. The stalled prefetch thread or threads are then reactivated.

Abstract translation: 处理器执行一个或多个预取线程和一个或多个主计算线程。 每个预取线程在主计算线程之前执行指令以检索主计算线程的数据，例如主计算线程在不久的将来可能使用的数据。 针对预取线程检索数据并存储在存储器中，例如从外部存储器读取并存储在缓冲器中的数据。 预取控制器确定存储器是否已满。 如果内存已满，缓存控制器至少停止一个预取线程。 停顿可以继续，直到至少一些数据从存储器传送到高速缓存以供至少一个主计算线程使用。 然后重新激活停滞的预取线程或线程。