公开(公告)号：US20240107661A1

公开(公告)日：2024-03-28

申请号：US18472051

申请日：2023-09-21

Applicant: KYOCERA Document Solutions Inc.

Inventor： Shotaro Ikegami

IPC: H05K1/02

CPC classification number: H05K1/0231 ,  H05K2201/09345 ,  H05K2201/09618 ,  H05K2201/09636 ,  H05K2201/10159 ,  H05K2201/10651

Abstract: A signal processing board includes a six-layer substrate. A plurality of signal transmission planes are formed in a first layer, a third layer, a fourth layer, and a sixth layer. A first ground plane is formed in a second layer. A first power supply plane is formed in a fifth layer and electrically connected to the first semiconductor element. A second power supply plane is formed in the fifth layer and electrically connected to the second semiconductor element. A second ground plane is formed in the fifth layer. A first bypass capacitor is electrically connected to the first power supply plane and the second ground plane. A second bypass capacitor is electrically connected to the second power supply plane and the second ground plane.

公开(公告)号：US20240074055A1

公开(公告)日：2024-02-29

申请号：US17899477

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Walter L. Moden ,  Stephen F. Moxham ,  Travis M. Jensen

IPC: H05K1/11 ,  H01L21/48 ,  H01L23/48 ,  H01L23/498 ,  H05K3/00 ,  H05K3/40

CPC classification number: H05K1/116 ,  H01L21/4846 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49838 ,  H05K3/0014 ,  H05K3/0047 ,  H05K3/4038 ,  H01L24/16 ,  H05K2201/09563 ,  H05K2201/09636

Abstract: Substrates with continuous slot vias are disclosed herein. In one embodiment, a substrate comprises a first design layer, a second design layer, and an intermediary layer between the first and second design layers. The substrate further includes first and second signaling vias extending vertically through the intermediary layer between the first and second design layers. The first and second signaling vias route first and second data signals, respectively, between the first and second design layers. The substrate further includes a slot via that is positioned between the first and second signaling vias within the intermediary layer and extends laterally within the intermediary layer along a path that passes between the first signaling via and the second signaling via. The slot via can have a continuous shape such that the slot via shields the first and second data signals on the first and second signaling vias from crosstalk with one another.

公开(公告)号：US20230363082A1

公开(公告)日：2023-11-09

申请号：US18348003

申请日：2023-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byeongkeol KIM ,  Eunseok HONG ,  Youngsun LEE

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/28 ,  H05K3/42 ,  H04M1/02 ,  H04B1/00

CPC classification number: H05K1/0219 ,  H05K1/028 ,  H05K1/118 ,  H05K3/28 ,  H05K3/429 ,  H04M1/0277 ,  H04B1/0053 ,  H05K2201/09636

Abstract: An electronic device is provided. The electronic device includes a housing including a first housing part and a second housing part movable with respect to the first housing part, and a circuit board positioned in the housing and including a first part bent in response to movement of the second housing part and a second part extending from the first part and more rigid than the first part, wherein the circuit board may comprise a flexible non-conductive film extending from the first part to the second part, a laminate structure including at least one conductive pattern positioned on the flexible non-conductive film, a coverlay extending from the first part to the second part, overlapping the laminate structure, and including an electromagnetic shielding material, and at least one conductive via positioned at the second part and electrically connecting the at least one conductive pattern and the coverlay.

公开(公告)号：US20230199940A1

公开(公告)日：2023-06-22

申请号：US17918384

申请日：2021-04-30

Applicant: Sumitomo Electric Industries, Ltd.

Inventor： Noriyoshi SUDA

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K1/0219 ,  H05K1/115 ,  H05K1/185 ,  H05K2201/09636

Abstract: A circuit module includes: a multilayer board having a plurality of first through-holes each penetrating at least one layer thereof; a plurality of high frequency components disposed in the plurality of first through-holes, respectively; and a plurality of shield parts individually surrounding the plurality of high frequency components. The multilayer board has a second through-hole penetrating at least a layer in which each high frequency component is disposed. Each of the plurality of shield parts includes a first conductor, a second conductor, and a third conductor. The first conductor and the second conductor sandwich the high frequency component in a lamination direction of the multilayer board. The third conductor is disposed in the second through-hole.

公开(公告)号：US20180053886A1

公开(公告)日：2018-02-22

申请号：US15680984

申请日：2017-08-18

Applicant: Nichia Corporation

Inventor： Akira Goto ,  Kunihito Sugimoto

IPC: H01L33/64 ,  H05K1/02 ,  H05K1/18 ,  H05K1/03 ,  H05K1/09 ,  F21V19/00 ,  H01L25/075 ,  H01L33/62

CPC classification number: H01L33/647 ,  F21V19/0025 ,  F21Y2115/10 ,  H01L25/0753 ,  H01L33/505 ,  H01L33/60 ,  H01L33/62 ,  H01L33/641 ,  H01L33/642 ,  H05K1/0204 ,  H05K1/0206 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/09 ,  H05K1/181 ,  H05K2201/0187 ,  H05K2201/09636 ,  H05K2201/10106 ,  H05K2201/10674

Abstract: A light emitting device includes a mounting board, a first light emitting element and a second light emitting element. The mounting board includes an insulator which includes a front face and a back face, a pair of front face wiring parts disposed on the front face of the insulator, a connection wiring part disposed on the front face of the insulator and spaced apart from the front face wiring parts, a pair of back face terminals disposed on the back face of the insulator, first interlayer wiring parts penetrating the insulator and electrically connecting the front face wiring parts and the back face terminals, and one or more second interlayer wiring parts embedded in the insulator to be in contact with the connection wiring part, and spaced apart from the back face terminals.

公开(公告)号：US09755391B2

公开(公告)日：2017-09-05

申请号：US14593735

申请日：2015-01-09

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Darko R. Popovic

IPC: H05K1/00 ,  H05K1/18 ,  H05K7/00 ,  H01R43/20 ,  H05K1/02 ,  H01L23/498 ,  H01L23/50 ,  H01L23/552

CPC classification number: H01R43/205 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/552 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K1/0228 ,  H05K1/0245 ,  H05K2201/09609 ,  H05K2201/09636

Abstract: Embodiments reduce crosstalk between electrical interconnects by offsetting pairs of electrical interconnects in an electrical system to produce a staggered interconnect pattern for which magnetic flux through a loop formed by a victim interconnect pair is effectively canceled. Magnetic field vectors generated by an aggressor pair of interconnects can pass through a loop-bounded surface defined by a victim pair of interconnects in the system. In the staggered interconnect pattern, the victim interconnect pair is offset with respect to the aggressor interconnect pair so that the field vectors passing through the victim pair's loop-bounded surface in one direction are substantially balanced by the field vectors passing through the victim pair's loop-bounded surface in the opposite direction, thereby minimizing the effect of the aggressor pair's magnetic field on the victim pair. Since crosstalk is proportional to the rate of change of the magnetic flux, reducing the magnetic flux can reduce the crosstalk.

公开(公告)号：US20170181270A1

公开(公告)日：2017-06-22

申请号：US15381301

申请日：2016-12-16

Applicant: Curtiss-Wright Controls, Inc.

Inventor： Michael Rose ,  Robert Sullivan

IPC: H05K1/02 ,  H05K3/40 ,  H05K3/20 ,  H05K1/11

CPC classification number: H05K1/0251 ,  H05K1/0216 ,  H05K1/024 ,  H05K1/0245 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/20 ,  H05K3/4038 ,  H05K2201/0187 ,  H05K2201/09063 ,  H05K2201/09227 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/1059

Abstract: A circuit board comprises a plurality of layers, first and second reference conductive vias extending in a vertical direction through at least a portion of the plurality of layers, first and second signal conductive vias extending in the vertical direction between and spaced apart in a horizontal direction from the first and second reference conductive vias through at least a portion of the plurality of layers, and a dielectric region extending in the vertical direction between the first and second signal conductive vias. An air via extends in the vertical direction through the dielectric region between the first and second signal conductive vias. An anti-pad extends in the horizontal direction between the first and second reference conductive vias and surrounding in the horizontal direction the first and second signal conductive vias, the air via, and the dielectric region.

公开(公告)号：US09583809B2

公开(公告)日：2017-02-28

申请号：US14509285

申请日：2014-10-08

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Noboru Kato ,  Satoshi Ishino ,  Jun Sasaki

IPC: H01P3/00 ,  H01P3/08 ,  H01P3/02 ,  H01P5/02 ,  H05K1/02

CPC classification number: H01P3/003 ,  H01P3/026 ,  H01P3/08 ,  H01P3/082 ,  H01P3/085 ,  H01P5/028 ,  H05K1/0225 ,  H05K1/0251 ,  H05K2201/09245 ,  H05K2201/09336 ,  H05K2201/09636 ,  H05K2201/097

Abstract: A high-frequency signal line includes a body with a first layer level and a second layer level; a signal line including a first line portion provided at the first layer level, a second line portion provided at the second layer level, and a first interlayer connection connecting the first line portion and the second line portion; a first ground conductor including a first ground portion provided at the first layer level; a second ground conductor including a second ground portion provided at the second layer level; and a second interlayer connection connecting the first ground portion and the second ground portion. A distance between the first interlayer connection and the second interlayer connection is not less than a maximum distance between the first line portion and the first ground portion and is not less than a maximum distance between the second line portion and the second ground portion.

Abstract translation: 高频信号线包括具有第一层级和第二层级的主体; 信号线，包括设置在第一层级的第一线部分，设置在第二层级的第二线部分和连接第一线部分和第二线部分的第一层间连接; 第一接地导体，包括设置在第一层级的第一接地部分; 第二接地导体，包括设置在第二层级的第二接地部分; 以及连接所述第一接地部和所述第二接地部的第二层间连接。 第一层间连接和第二层间连接之间的距离不小于第一线部分和第一接地部分之间的最大距离，并且不小于第二线路部分和第二接地部分之间的最大距离。

公开(公告)号：US09545003B2

公开(公告)日：2017-01-10

申请号：US14092039

申请日：2013-11-27

Applicant: Madhumitha Rengarajan ,  Jan De Geest ,  Stephen B. Smith ,  Stefaan Hendrik Jozef Sercu

Inventor： Madhumitha Rengarajan ,  Jan De Geest ,  Stephen B. Smith ,  Stefaan Hendrik Jozef Sercu

IPC: H05K1/11 ,  H05K1/02

CPC classification number: H05K1/116 ,  H05K1/0222 ,  H05K1/0251 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2203/0207 ,  H05K2203/0242

Abstract: An electrical connector footprint on a printed circuit board (PCB) can include vias and antipads surrounding those vias. While conventional antipads surrounding vias are large in order to improve impedance of the PCB, the presence of the antipads can compromise the integrity of the ground plane and can permit cross talk to arise between differential pairs on different layers in the PCB. Antipads can be constructed and arranged so as to limit cross talk between layers in a PCB, while also maximizing impedance.

Abstract translation: 印刷电路板（PCB）上的电连接器封装可以包括围绕这些通孔的通孔和反电极片。 虽然围绕通孔的常规反焊盘较大以改善PCB的阻抗，但是反焊盘的存在可能损害接地平面的完整性，并且可以允许在PCB中的不同层上的差分对之间产生串扰。 可以构建和布置反阻臂以限制PCB中的层之间的串扰，同时还使阻抗最大化。

公开(公告)号：US09159625B1

公开(公告)日：2015-10-13

申请号：US13015445

申请日：2011-01-27

Applicant: Seung Jae Lee ,  Sang Won Kim ,  Ki Cheol Bae ,  Ji Heon Yu

Inventor： Seung Jae Lee ,  Sang Won Kim ,  Ki Cheol Bae ,  Ji Heon Yu

IPC: H01L23/48 ,  H01L21/78

CPC classification number: H01L21/7806 ,  H01L23/5226 ,  H01L23/66 ,  H05K1/0222 ,  H05K1/0251 ,  H05K1/115 ,  H05K2201/09636

Abstract: Disclosed is a semiconductor device. For instance, the semiconductor device includes a main via formed on a dielectric and a ground via formed in a circular arc shape and spaced apart from the main via. The semiconductor device is superior in electric characteristics such as insertion loss or reflection loss and allows efficient use of space.

Abstract translation: 公开了一种半导体器件。 例如，半导体器件包括形成在电介质上的主通路和形成为圆弧形并与主通路间隔开的接地通孔。 半导体器件的电气特性如插入损耗或反射损耗优异，并且可以有效地利用空间。