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    Method of forming a monolayer of particles having at least two different sizes, and products formed thereby
    191.
    发明申请
    Method of forming a monolayer of particles having at least two different sizes, and products formed thereby 失效
    形成具有至少两种不同尺寸的颗粒的单层的方法，以及由此形成的产品

    公开(公告)号：US20030180508A1

    公开(公告)日：2003-09-25

    申请号：US10388441

    申请日：2003-03-17

    Inventor： Ciaran Bernard McArdle ,  Rory Brian Barnes

    IPC: B32B003/00

    CPC classification number: H01R4/04 ,  G03F7/34 ,  H01L2224/293 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/10253 ,  H05K3/323 ,  H05K2201/083 ,  H05K2201/09945 ,  H05K2203/0769 ,  H05K2203/104 ,  Y10T428/24802 ,  H01L2924/00

    Abstract: The invention provides a method of forming a monolayer of substantive particles including the steps of applying to a substrate a curable composition having substantive particles contained therein, the substantive particles having a particle size on at least one dimension thereof of at least 1 micrometer and being in two or more groups of different sizes; exposing the substantive particle-containing curable composition to a source of energy suitable for effecting polymerization of the curable composition for a sufficient time to effect polymerization of a layer of the curable composition having a thickness of no more than 50% of the height of the largest substantive particles; and optionally, removing uncured curable composition. The invention also provides a method of forming a monolayer of substantive particles in a non-random array where the curable composition comprises a ferrofluid composition. The latter method further comprises the step of subjecting the particle-containing curable ferrofluid composition to a magnetic field for a sufficient time to array the particles in a non-random manner in the composition prior to the exposure.

    Abstract translation: 本发明提供了一种形成单层实质性颗粒的方法，包括以下步骤：将具有其中所含的实质性颗粒的可固化组合物施用于基材，所述实体颗粒的至少一个尺寸的颗粒尺寸至少为1微米， 两组或两组以上不同大小; 将含有实质的含颗粒的可固化组合物暴露于适于实现可固化组合物聚合足够时间的能量源，以实现可固化组合物层的厚度不超过最大厚度的50％ 实质粒子 并且任选地，除去未固化的可固化组合物。 本发明还提供了以非随机阵列形成单层实质性颗粒的方法，其中可固化组合物包含铁磁流体组合物。 后一种方法还包括以下步骤：使含有颗粒的可固化铁磁体组合物经历足够的时间以在曝光之前以非随机方式将组合物排列在组合物中。

    Method of connecting a unit under test in a wireless test fixture
    193.
    发明授权
    Method of connecting a unit under test in a wireless test fixture 失效
    在无线测试夹具中连接被测单元的方法

    公开(公告)号：US6047469A

    公开(公告)日：2000-04-11

    申请号：US968960

    申请日：1997-11-12

    Applicant: L. Jack Luna

    Inventor： L. Jack Luna

    IPC: G01R1/04 ,  H05K1/00 ,  H05K3/42 ,  H05K3/36

    CPC classification number: G01R1/0408 ,  H05K1/0287 ,  H05K1/0298 ,  H05K2201/09454 ,  H05K2201/0949 ,  H05K2201/09945 ,  H05K3/429 ,  Y10T29/49126 ,  Y10T29/49165

    Abstract: A multilayer printed circuit board has prefabricated inner signal layers and unfinished top and bottom layers for customizing the board for a particular test installation. Each signal layer has a predetermined arrangement of circuits, each circuit having first and second via pads at opposite ends of the circuit. The first via pads form a virtual grid for selective connection to test points of a unit under test. The top layer is processed to provide a test pad aligned with each test point on a unit under test, a via pad for each test pad which is aligned with the closest available virtual grid via, and a connecting trace between each test pad and the associated via pad. Plated through holes are drilled through the board at each outer layer via pad for connection to the aligned virtual grid via. Similar processing of the bottom layer connects the via pad at the opposite end of each assigned inner layer circuit to an interface pad for connection to a respective terminal of automated test equipment.

    Abstract translation: 多层印刷电路板具有预制的内部信号层和未完成的顶层和底层，用于定制用于特定测试装置的板。 每个信号层具有预定的电路布置，每个电路在电路的相对端具有第一和第二通孔焊盘。 第一通孔焊盘形成虚拟栅格，用于选择性地连接到被测单元的测试点。 处理顶层以提供与待测单元上的每个测试点对准的测试垫，用于每个测试垫的通孔垫，其与最接近的可用虚拟网格通孔对准，以及每个测试垫与相关联的连接迹线 通过垫。 通过焊盘在每个外层穿过板上钻出通孔，以连接到对准的虚拟栅格通孔。 底层的类似处理将每个分配的内层电路的相对端的通孔焊盘连接到用于连接到自动测试设备的相应端子的接口焊盘。

    Method of making multi-layer circuit
    196.
    发明授权
    Method of making multi-layer circuit 失效
    制作多层电路的方法

    公开(公告)号：US5640761A

    公开(公告)日：1997-06-24

    申请号：US478420

    申请日：1995-06-07

    Applicant: Thomas H. DiStefano ,  Igor Y. Khandros ,  Gary W. Grube

    Inventor： Thomas H. DiStefano ,  Igor Y. Khandros ,  Gary W. Grube

    IPC: H01L21/48 ,  H01L23/538 ,  H05K1/00 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46 ,  H05K3/36

    CPC classification number: H05K3/462 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5385 ,  H01R12/523 ,  H05K1/0287 ,  H05K1/029 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0298 ,  H05K2201/0195 ,  H05K2201/0305 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2201/10666 ,  H05K2203/175 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4623 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

    Abstract: Multilayer circuit assemblies are made by stacking circuit panels having contacts on their top surfaces, through conductors extending between top and bottom surfaces and terminals connected to the bottom end of each through conductor. The terminals and contacts are arranged so that when the panels are stacked the terminals on the bottom of one panel are in alignment with the contacts on the top surface of the immediately underlying panel. The panels are selectively treated on their top and/or bottom surfaces so as to selectively disconnect or connect each contact to a terminal on the bottom surface of the same panel. For example, the top surface of the panel may be selectively etched to disconnect a contact from one through conductor and hence from the associated terminal. The aligned terminals and contacts are nonselectively connected to one another at each interface so that wherever a terminal and contact on adjacent panels are aligned with one another there are connected to one another. This forms composite vertical conductors extending through a plurality of the panels. The selective treatment of the panel top and bottom surfaces provides selective interruptions in the vertical conductors. A circuit panel precursor having the through conductors and methods of making the same are also provided.

    Abstract translation: 多层电路组件通过在其顶表面上具有接触的电路板堆叠，通过在顶表面和底表面之间延伸的导体以及连接到每个贯通导体的底端的端子而制成。 端子和触点被布置成使得当面板堆叠时，一个面板的底部上的端子与紧邻的底板的顶表面上的触点对准。 在其顶表面和/或底表面上选择性地处理这些面板，以便选择性地将每个接触件断开或连接到同一面板的底表面上的端子。 例如，可以选择性地蚀刻面板的顶表面以将接触从一个导体断开，并因此从相关联的端子断开。 对准的端子和触点在每个接口处彼此非选择性地连接，使得相邻面板上的端子和触点彼此对准的位置彼此连接。 这形成延伸穿过多个面板的复合垂直导体。 面板顶部和底部表面的选择性处理在垂直导体中提供选择性的中断。 还提供了具有贯通导体的电路板前体及其制造方法。

    Multi-layer circuit construction methods and structures with customization features and components for use therein
    197.
    发明授权
    Multi-layer circuit construction methods and structures with customization features and components for use therein 失效
    多层电路构造方法和结构，具有用于其中的定制特征和组件

    公开(公告)号：US5583321A

    公开(公告)日：1996-12-10

    申请号：US443706

    申请日：1995-05-15

    Applicant: Thomas H. DiStefano ,  Igor Y. Khandros ,  Gary W. Grube

    Inventor： Thomas H. DiStefano ,  Igor Y. Khandros ,  Gary W. Grube

    IPC: H01L21/48 ,  H01L23/538 ,  H05K1/00 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46 ,  H05K1/02

    CPC classification number: H05K3/462 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5385 ,  H01R12/523 ,  H05K1/0287 ,  H05K1/029 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0298 ,  H05K2201/0195 ,  H05K2201/0305 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2201/10666 ,  H05K2203/175 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4623 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

    Abstract: Multilayer circuit assemblies are made by stacking circuit panels having contacts on their top surfaces, through conductors extending between top and bottom surfaces and terminals connected to the bottomend of each through conductor. The terminals and contacts are arranged so that when the panels are stacked the terminals on the bottom of one panel are in alignment with the contacts on the top surface of the immediately underlying panel. The panels are selectively treated on their top and/or bottom surfaces so as to selectively disconnect or connect each contact to a terminal on the bottom surface of the same panel. For example, the top surface of the panel may be selectively etched to disconnect a contact from one through conductor and hence from the associated terminal. The aligned terminals and contacts are nonselectively connected to one another at each interface so that wherever a terminal and contact on adjacent panels are aligned with one another there are connected to one another. This forms composite vertical conductors extending through a plurality of the panels. The selective treatment of the panel top and bottom surfaces provides selective interruptions in the vertical conductors. A circuit panel precursor having the through conductors and methods of making the same are also provided.

    Abstract translation: 多层电路组件通过在其顶表面上堆叠具有触点的电路板，通过在顶表面和底表面之间延伸的导体以及连接到每个贯通导体的底端的端子而形成。 端子和触点被布置成使得当面板堆叠时，一个面板的底部上的端子与紧邻的底板的顶表面上的触点对准。 在其顶表面和/或底表面上选择性地处理这些面板，以便选择性地将每个接触件断开或连接到同一面板的底表面上的端子。 例如，可以选择性地蚀刻面板的顶表面以将接触从一个导体断开，并因此从相关联的端子断开。 对准的端子和触点在每个接口处彼此非选择性地连接，使得相邻面板上的端子和触点彼此对准的位置彼此连接。 这形成延伸穿过多个面板的复合垂直导体。 面板顶部和底部表面的选择性处理在垂直导体中提供选择性的中断。 还提供了具有贯通导体的电路板前体及其制造方法。

    Multi-Layer circuit construction method and structure
    198.
    发明授权
    Multi-Layer circuit construction method and structure 失效
    多层电路构造方法与结构

    公开(公告)号：US5570504A

    公开(公告)日：1996-11-05

    申请号：US393165

    申请日：1995-02-21

    Applicant: Thomas H. DiStefano ,  Igor Y. Khandros ,  Gary W. Grube

    Inventor： Thomas H. DiStefano ,  Igor Y. Khandros ,  Gary W. Grube

    IPC: H01L21/48 ,  H01L23/538 ,  H05K1/00 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46 ,  H05K3/36

    CPC classification number: H05K3/462 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5385 ,  H01R12/523 ,  H05K1/0287 ,  H05K1/029 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0298 ,  H05K2201/0195 ,  H05K2201/0305 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2201/10666 ,  H05K2203/175 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4623 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

    Abstract: Multilayer circuit assemblies are made by stacking circuit panels having contacts on their top surfaces, through conductors extending between top and bottom surfaces and terminals connected to the bottomend of each through conductor. The terminals and contacts are arranged so that when the panels are stacked the terminals on the bottom of one panel are in alignment with the contacts on the top surface of the immediately underlying panel. The panels are selectively treated on their top and/or bottom surfaces so as to selectively disconnect or connect each contact to a terminal on the bottom surface of the same panel. For example, the top surface of the panel may be selectively etched to disconnect a contact from one through conductor and hence from the associated terminal. The aligned terminals and contacts are nonselectively connected to one another at each interface so that wherever a terminal and contact on adjacent panels are aligned with one another there are connected to one another. This forms composite vertical conductors extending through a plurality of the panels. The selective treatment of the panel top and bottom surfaces provides selective interruptions in the vertical conductors. A circuit panel precursor having the through conductors and methods of making the same are also provided.

    Abstract translation: 多层电路组件通过在其顶表面上堆叠具有触点的电路板，通过在顶表面和底表面之间延伸的导体以及连接到每个贯通导体的底端的端子而形成。 端子和触点被布置成使得当面板堆叠时，一个面板的底部上的端子与紧邻的底板的顶表面上的触点对准。 在其顶表面和/或底表面上选择性地处理这些面板，以便选择性地将每个接触件断开或连接到同一面板的底表面上的端子。 例如，可以选择性地蚀刻面板的顶表面以将接触从一个导体断开，并因此从相关联的端子断开。 对准的端子和触点在每个接口处彼此非选择性地连接，使得相邻面板上的端子和触点彼此对准的位置彼此连接。 这形成延伸穿过多个面板的复合垂直导体。 面板顶部和底部表面的选择性处理在垂直导体中提供选择性的中断。 还提供了具有贯通导体的电路板前体及其制造方法。

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