Abstract:
A protection circuit 116 for a computer system 110 having PCI expansion cards 120 and PCI expansion slots 118 with multiple power rails 312,322;314,328;318,324;320,326 for supplying power to the PCI expansion cards is disclosed. The protection circuit includes a current monitor 212 that monitors the current levels drawn by the PCI expansion card at each power rail. An inrush current controller 330/332/334 controls the initial current applied to each of the power rails when an expansion card is initially inserted into an expansion slot. A voltage monitor 212 monitors the voltage levels applied to selected power rails and a disconnector 210 disconnects the power to the PCI expansion slot when either the current level drawn by the PCI expansion card at any of the power rails goes beyond a selected range or when the voltage levels at any of the selected monitored power rails are below a selected threshold, or when commanded to by the computer system.
Abstract:
The present invention relates to circuitry for selecting a master battery pack for supplying power to a computer system capable of incorporating multiple battery packs. A bi-directional master battery signal is communicated to the microcontroller of each installed battery pack and arbitration circuitry contained within the host computer system. The master battery signal operates in conjunction with a serial communications interface between each of the installed battery packs and the host computer system. Battery status information is communicated to the host computer system via the serial communications interface, and the host computer system then selects a master battery pack. The battery pack selected to be the master asserts the master battery signal while all other battery packs monitor this signal waiting for it to be deasserted. Other battery packs utilize the master battery signal to control their own charge and discharge circuitry. Deassertion of the master battery signal denotes that the master battery pack is no longer capable of supplying power to the host computer system and the master battery pack arbitration process is repeated.
Abstract:
A handheld computer which contains an LCD display having a digitizing surface to allow pen input. Internal storage takes several forms, such as a large flash ROM area, battery-backed up RAM and an optional hard disk drive. Several alternative communication paths are available, such as the previously mentioned modem, a parallel printer port, a conventional serial port, a cradle assembly connected to the host computer, and various wireless short distance techniques such as radio frequency or infrared transmission. The computer can readily communicate with other sources, particularly to a host desktop computer, to allow automated synchronization of information between the host and the handheld system. Preferably the remote synchronization is performed at several user selectable levels. When the handheld computer is in a cradle and actively connected to the host computer, automatic capture of updated data in the host computer is performed. Several synchronization tehcniqques are utilized to keep track of different types of files. In addition, while communication is established the handheld computer can enter a remote control mode, allowing the user access to files and applications not included in the handheld computer.
Abstract:
An audio power management system for a computer eliminates audible noise associated with the cycling of power to an audio amplifier for a computer. A diode is connected between the power supply rail and the power input to the audio amplifier. One or more decoupling capacitors is provided at the power input to the audio amplifier to insulate the audio amplifier from fluctuations at the power supply. The apparatus mutes the amplifier for a brief period shortly after power becomes available and mutes the amplifier immediately when power is removed to eliminate transient noises. In one embodiment, the muting of the audio amplifier is accomplished by FET switches. In a second embodiment, the muting of the audio amplifier is accomplished by analog switches. Additionally, the audio power management system eliminates audible noise associated with the waking-up or putting the computer to sleep. The audio system asserts a speaker mute signal before power is removed from the amplifier to reduce transient conditions. During power up, the speaker mute signal is applied to the amplifier for a period after power has been applied to the amplifier. This control is economically accomplished using a minimal number of digital outputs.
Abstract:
Circuitry for drawing lines includes a video memory for storing pixel data and circuitry for generating a sequence of addresses defining a line of pixels in the video memory. A first memory stores a sequence of pattern units corresponding to the generated sequence of addresses. A second memory stores a value indicating a current pattern unit. Writing circuitry writes to the video memory at a generated address responsive to a current pattern unit. A third memory stores a control value which is accessed by update circuitry for updating the second memory to indicate the next pattern unit. The update circuitry may selectively update the second memory to the sequential pattern unit or reset the second memory to a predetermined pattern unit.
Abstract:
A hot spare boot circuit that automatically switches from a non-operational CPU to an operational CPU for powering up the computer system. In the multiprocessor computer system, a first CPU is designated to perform power on operations. If the first CPU fails, which is determined when a dead man counter in the hot spare boot circuit times out, the hot spare circuit ensures that the first CPU is in a disabled state. Next, the hot spare boot circuit identifies an operational second CPU, reinitializing certain ID information as necessary such that the second CPU can properly perform power on operations. The hot spare boot then awakens the second CPU, using a startup interprocessor interrupt in one embodiment, or simply negating the hard reset of the second CPU in a second embodiment. The second CPU then proceeds to perform the power on functions.
Abstract:
A system for performing on-line reconfiguration of a disk array in which a source logical volume is reconfigured to a destination logical volume. Disk array configuration is invoked if a new physical drive is inserted, or a drive is removed. Reconfiguration can also be performed if the user desires to change the configuration of a particular logical volume, such as its stripe size. The disk array reconfiguration is run as a background task by firmware on a disk controller board. The reconfigure task first moves data from the source logical volume to a posting memory such as RAM memory. The reconfigure task operates one stripe at a time, with the stripe size being that of the destination logical volume. Once a stripe of data is moved into the posting memory, it is written back to corresponding locations in the destination logical volume. The reconfigure task continues until all data in the source logical volume have been moved into the destination logical volume. While the reconfigure task is working on a particular logical volume, data remains accessible to host write and read requests.
Abstract:
An apparatus is described for providing power management of a computer. The apparatus includes circuitry configured to assert a power down signal when a low power mode is to be entered and to de-assert the power down signal when the low power mode is to be exited. An audio amplifier has a power input and a mute input, and a switch is connected to the power input and configured to selectively supply power to the power input. A power down circuit is provided responsive to the power down signal and connected to the mute input and the switch such that when the power down signal is asserted, the power down circuit activates the mute input and subsequently closes the switch, and when the power down signal is de-asserted, the power down circuit opens the switch and subsequently deactivates the mute input.
Abstract:
A page wide piezoelectric ink jet print engine and a method of manufacturing the same. The page wide ink jet print engine includes lower and upper body parts, each formed from piezoelectric material and having a plurality of generally parallel, spaced projections. Lower side surfaces of the projections of the lower body part are conductively mounted to corresponding bottom side surfaces of the projections of the upper body part to define a plurality of generally parallel, axially extending ink-carrying channels from which ink may be ejected. The lower and upper body parts are then circumferentially poled such that, for the lower body part, first and second polarization fields respectively extend between the top side surface of each one of the projections and top side surfaces of first and second projections adjacent thereto and, for the upper body part first and second polarization fields respectively extend between the bottom side surface of each one of the projections and bottom side surfaces of first and second projections adjacent thereto. By applying voltage to selective ones of the projections, the channels may be selectively expanded to draw ink from an associated ink delivery system and compressed to cause the ejection of a droplet of ink therefrom.