公开(公告)号：WO1997050117A1

公开(公告)日：1997-12-31

申请号：PCT/US1997003097

申请日：1997-02-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  SHEN, Lewis, N.

IPC: H01L21/321

CPC classification number: G02B27/0031 ,  A61L27/18 ,  A61L27/56 ,  A61L2400/06 ,  G03F7/40 ,  H01L21/0273 ,  H01L21/32139 ,  C08L67/04

Abstract: Adverting to Fig. 5, a passivation coating (40) is formed on a phtoresist mask (14) to increase the resistance of the mask during subsequent etching of an underlying conductive layer (12, 13) to form a pattern of sub-half micron conductive lines. In an embodiment of the invention, the passivation coating is formed by exposing the mask to a plasma containing nitrogen. The passivation coating maintains the substantially vertical mask profile during subsequent etching, such as high density plasma etching, thereby improving the dimensional integrity of the sub-half micron conductive lines.

Abstract translation: 广告图 如图5所示，钝化涂层（40）形成在钝化掩模（14）上，以在随后蚀刻下面的导电层（12,13）期间增加掩模的电阻，以形成半微米的导电线图案。 在本发明的一个实施例中，通过将掩模暴露于含有氮的等离子体来形成钝化涂层。 钝化涂层在后续蚀刻（例如高密度等离子体蚀刻）期间保持基本垂直的掩模轮廓，从而改善了次半微米导电线的尺寸完整性。

公开(公告)号：WO1997050112A1

公开(公告)日：1997-12-31

申请号：PCT/US1997002389

申请日：1997-02-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GARDNER, Mark, I. ,  WRISTERS, Derick, J. ,  FULFORD, H., Jim, Jr.

IPC: H01L21/02

CPC classification number: G03F7/70466 ,  G03F7/2022 ,  G03F7/70475 ,  H01L21/0334

Abstract: A method of selectively exposing a material over a substrate is disclosed. The method includes forming a material over a semiconductor substrate, forming a photosensitive layer over the material, projecting a first image pattern onto the photosensitive layer that defines a first boundary for the material, projecting a second image pattern onto the photosensitive layer after projecting the first image pattern such that the second image pattern partially overlaps the first image pattern and defines a second boundary for the material, and removing portions of the photosensitive layer corresponding to the first and second image patterns. Preferably, the first and second image patterns are essentially identical to and laterally shifted with respect to one another. In this manner, the photosensitive layer selectively exposes the material adjacent to the first and second boundaries while covering the material between the first and second boundaries, and the distance between the first and second boundaries decreases as the overlap between the first and second image patterns decreases. Advantageously, the first and second boundaries can be closer than the minimum resolution of the photolithographic system used to pattern the photosensitive layer.

Abstract translation: 公开了一种在衬底上选择性地暴露材料的方法。 该方法包括在半导体衬底上形成材料，在材料上形成感光层，将第一图案图案投射到限定材料的第一边界的光敏层上，将第一图像图案投射到感光层上， 图像图案，使得第二图像图案部分地与第一图像图案重叠并且限定材料的第二边界，以及去除与第一和第二图像图案相对应的感光层的部分。 优选地，第一和第二图像图案基本上彼此相同并且相对于彼此横向移位。 以这种方式，感光层选择性地暴露与第一和第二边界相邻的材料，同时覆盖第一和第二边界之间的材料，并且第一和第二边界之间的距离随着第一和第二图像图案之间的重叠减小而减小 。 有利地，第一和第二边界可以比用于图案感光层的光刻系统的最小分辨率更接近。

公开(公告)号：WO1997050089A1

公开(公告)日：1997-12-31

申请号：PCT/US1997001822

申请日：1997-01-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  BILL, Colin, Stewart ,  GUTALA, Ravi, Prakash ,  ZHOU, Qimeng (Derek) ,  SU, Jonathan, Shichang

IPC: G11C11/56

CPC classification number: G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2211/5622 ,  G11C2211/5634 ,  G11C2211/5642

Abstract: An improved reading structure (110) for performing a read operation in an array of multiple bits-per-cell flash EEPROM memory cells is provided. A memory core array (12) includes a plurality of memory cells, each being previously programmed to one of a plurality of memory conditions defined by memory core threshold voltages. A reference cell array (22) includes a plurality of reference core cells which are selected together with a selected core cell and provides selectively one of a plurality of reference cell bit line voltages defined by reference cell threshold voltages. Each of the reference cells are previously programmed at the same time as when the memory core cells ar being programmed. A precharge circuit (36) is used to precharge the array bit lines and the reference bit lines to a predetermined potential. A detector circuit (28) is responsive to the bit line voltages of the reference cells for generating strobe signals. A reading circuit (26) is responsive to the strobe signals for comparing the memory core threshold voltage with each of the reference cell threshold voltages.

Abstract translation: 提供了一种改进的读取结构（110），用于以多个比特单元的闪存EEPROM存储单元的阵列执行读取操作。 存储器核心阵列（12）包括多个存储器单元，每个存储器单元预先被编程为由存储器核心阈值电压定义的多个存储器条件中的一个。 参考单元阵列（22）包括与选定的核心单元一起选择的多个参考核心单元，并且选择性地提供由参考单元阈值电压限定的多个参考单元位线电压中的一个。 在存储核心单元被编程的同时，每个参考单元被预先编程。 预充电电路（36）用于将阵列位线和参考位线预充电至预定电位。 检测器电路（28）响应于参考单元的位线电压以产生选通信号。 读取电路（26）响应于选通信号，用于将存储器核心阈值电压与每个参考单元阈值电压进行比较。

公开(公告)号：WO1997049120A1

公开(公告)日：1997-12-24

申请号：PCT/US1997001705

申请日：1997-02-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  TRIPSAS, Nicholas, H.

IPC: H01L21/265

CPC classification number: H01L21/2652 ,  B26F1/384 ,  H01L21/823418 ,  H01L29/0847 ,  H01L29/456

Abstract: An improved process for forming shallow arsenic-doped source/drain regions in MOS devices utilizes a two-step arsenic implant which lowers the surface arsenic concentration while maintaining sharp junction profile and desired junction depth. Minimizing the excess arsenic in the surface region improves silicidation characteristics.

Abstract translation: 用于在MOS器件中形成浅砷掺杂源/漏区的改进方法利用两步砷注入，其降低表面砷浓度，同时保持尖锐的结形态和期望的结深度。 使表面区域中的过量砷最小化提高了硅化物的特性。

公开(公告)号：WO1997047115A1

公开(公告)日：1997-12-11

申请号：PCT/US1997001857

申请日：1997-02-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  SINGH, Alok ,  ROY, Rajat

IPC: H04L29/06

CPC classification number: H04L29/06 ,  H04L49/90

Abstract: A method of precisely identifying the end of packet location in a memory device. A first and second memory location in the memory device are reserved and a sequence of data is written into the memory device in sequential memory locations. When the last of the sequence of data is written into memory, the memory location is written into the first reserved memory location. The second memory location is written to show that the end of packet has been written into memory.

Abstract translation: 一种精确识别存储器件中包位置结束的方法。 存储器设备中的第一和第二存储器位置被保留，并且在顺序存储器位置中将一系列数据写入存储器件。 当最后一个数据序列被写入存储器时，存储器位置被写入第一保留存储器位置。 第二个内存位置被写入以显示分组的结束已被写入存储器。

公开(公告)号：WO1997047036A1

公开(公告)日：1997-12-11

申请号：PCT/US1997002513

申请日：1997-02-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  BANDYOPADHYAY, Basab ,  FULFORD, H., Jim, Jr. ,  DAWSON, Robert ,  HAUSE, Fred, N. ,  MICHAEL, Mark, W. ,  BRENNAN, William, S.

IPC: H01L21/768

CPC classification number: H01L21/76807 ,  H01L21/768 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors (12, 14), wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects. The conductors and vias are made by a damascene process. By staggering every other interconnect line in the densely patterned areas, the interconnects are capable of carrying a larger amount of current with minimal capacitive coupling therebetween.

Abstract translation: 提供了一种改进的多级互连结构。 互连结构包括多个级别的导体（12,14），其中一个层上的导体相对于另一层上的导体交错。 在密集间隔的互连区域中，插入的导体被拉至不同的高度级以减小互连之间的电容耦合。 导体和通孔由镶嵌工艺制成。 通过交错密集图案化区域中的每隔一个互连线，互连能够承载更大量的电流并且在其间具有最小的电容耦合。

公开(公告)号：WO1997044738A1

公开(公告)日：1997-11-27

申请号：PCT/US1997008358

申请日：1997-05-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GEPHARDT, Douglas, D. ,  SCHMIDT, Rodney, W.

IPC: G06F13/24

CPC classification number: G06F13/24

Abstract: A multiprocessing computer system which includes an interrupt controller coupled to an expansion bus. The programmable interrupt controller has multiple storage locations at the same address for multiple CPUs. The CPUs are coupled to a host bus which in turn is coupled to the expansion bus by means of a bus bridge. An arbiter is coupled to the host bus for arbitrating bus mastership amongst the CPUs. CPU host owner identification for access to the storage locations is transferred across bus bridge to the programmable interrupt controller synchronized with the buffered address and data.

Abstract translation: 一种多处理计算机系统，其包括耦合到扩展总线的中断控制器。 可编程中断控制器在多个CPU的同一地址具有多个存储位置。 CPU耦合到主机总线，主机总线又通过总线桥耦合到扩展总线。 仲裁器耦合到主机总线，用于仲裁CPU之间的总线主控权。 用于访问存储位置的CPU主机所有者标识通过总线桥传输到与缓冲的地址和数据同步的可编程中断控制器。

公开(公告)号：WO1997043714A1

公开(公告)日：1997-11-20

申请号：PCT/US1997008650

申请日：1997-05-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  SHARMA, Puneet ,  FAVOR, John, Gregory

IPC: G06F12/10

CPC classification number: G06F12/1054 ,  G06F12/0897

Abstract: Table walk logic (314, 350) and a second level access logic (410) are tightly coupled to each other in a second level control unit (210) that can operate in one of two modes, a translate mode that uses the table walk logic (314, 350) and an access mode that uses the second level access logic (410). In the translate mode, the second level control unit (210) uses the table walk logic (314, 350) for automatic translation of a virtual address to a corresponding physical address. In the access mode, the second level control unit (210) allows a word to be loaded from or stored into a given physical address. The second level control unit (210) prioritizes operations in the two modes e.g. performs an operation in the access mode prior to performance of an operation in the translate mode. The table walk logic (314, 350) and the second level access logic (410) can be integrated together into a single state machine, so that operations in the two modes are mutually exclusive and indivisible with respect to each other. Tight coupling of the two logics fundamentally enhances address translation circuitry, e.g. saves space and increases speed, as compared to prior art devices. Such tight coupling also eliminates an access into the first level cache for address translation, eliminates pollution of the first level cache by table entries and also reduces contention for the first level cache.

Abstract translation: 表行走逻辑（314,350）和第二级访问逻辑（410）在能够以两种模式之一操作的第二级别控制单元（210）中彼此紧密耦合，使用表格逻辑 （314,350）以及使用所述第二级访问逻辑（410）的访问模式。 在转换模式中，第二级控制单元（210）使用表行走逻辑（314,350）将虚拟地址自动转换为对应的物理地址。 在访问模式中，第二级控制单元（210）允许将字从该寄存器中加载或存储到给定的物理地址中。 第二电平控制单元（210）对两种模式中的操作进行优先排序。 在转换模式下执行操作之前在访问模式下执行操作。 台行逻辑（314,350）和第二级访问逻辑（410）可以集成在一起成为单个状态机，使得两种模式中的操作彼此相互排斥且不可分离。 两种逻辑的紧密耦合从根本上增强了地址转换电路，例如， 与现有技术的装置相比，节省空间并增加速度。 这种紧密耦合还消除了访问第一级缓存以进行地址转换，消除了表条目对第一级高速缓存的污染，并且还减少了第一级高速缓存的争用。

公开(公告)号：WO1997041596A1

公开(公告)日：1997-11-06

申请号：PCT/US1997002493

申请日：1997-02-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GARDNER, Mark, I. ,  HAUSE, Fred, N. ,  CHANG, Kuang-Yeh

IPC: H01L21/76

CPC classification number: H01L21/3144 ,  H01L21/3185 ,  H01L21/76224 ,  Y10S148/05

Abstract: A method of forming an improved isolation trench between active regions within the semiconductor substrate. The improved method incorporates a trench liner having a nitrogen content of approximately 0.5 to 2.0 percent. A pad layer is formed on a silicon substrate and a nitride layer is formed on the pad layer. Thereafter, a photoresist layer is patterned on the silicon nitride layer such that regions of the nitride layer are exposed where an isolation trench will subsequently be formed. Next, the exposed regions of the nitride layer and the pad layer situated below the exposed regions of the nitride layer are etched away to expose regions of the silicon substrate. Subsequently, isolation trenches are etched into the silicon substrate with a dry etch process. A trench liner is then formed and nitrogen incorporated into the trench liner. Incorporation of nitrogen into the trench liner can be accomplished by either forming the trench liner in the presence of a nitrogen bearing ambient or by forming a pure SiO2 trench liner and subsequently implanting the SiO2 trench liner with nitrogen. After formation of the nitrogenated trench liner, the trench is filled with a dielectric preferably comprised of a CVD oxide. Thereafter, the CVD fill dielectric is planarized and the nitride layer is stripped away.

Abstract translation: 一种在半导体衬底内的有源区之间形成改进的隔离沟槽的方法。 改进的方法包括氮含量为约0.5至2.0％的沟槽衬垫。 在硅衬底上形成衬垫层，并在衬垫层上形成氮化物层。 此后，在氮化硅层上图案化光致抗蚀剂层，使得随后将形成隔离沟槽的氮化物层的区域被暴露。 接下来，蚀刻掉位于氮化物层的暴露区域之下的氮化物层和焊盘层的暴露区域以暴露硅衬底的区域。 随后，用干蚀刻工艺将隔离沟槽蚀刻到硅衬底中。 然后形成沟槽衬垫，并且氮结合到沟槽衬里中。 通过在存在氮气环境的情况下形成沟槽衬垫或通过形成纯的SiO 2沟槽衬垫并随后用氮气注入SiO 2沟槽衬垫，可以将氮掺入到沟槽衬里中。 在形成氮化沟槽衬垫之后，用优选由CVD氧化物构成的电介质填充沟槽。 此后，CVD填充电介质被平坦化，并且氮化物层被剥离。

公开(公告)号：WO1997037379A1

公开(公告)日：1997-10-09

申请号：PCT/US1997002512

申请日：1997-02-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  TOPRAE, Anthony, John ,  BARNETT, Gerald

IPC: H01L21/66

CPC classification number: B24B37/013 ,  H01L22/26

Abstract: A laser interferometry technique is used to measure the thickness of deposits on the wall of an etching chamber. The measurement of deposit thickness on an etching chamber wall furnishes an accurate and useful parameter for quantifying the condition and state of an etch chamber. The measurement of deposit thickness on an etching chamber wall also supplies a parameter that is measured dynamically, over time and without interruption, while semiconductor wafers are processed, so that the need for cleaning maintenance is predicted before production loss occurs but without interruption of fabrication processing.

Abstract translation: 激光干涉测量技术用于测量蚀刻室壁上沉积物的厚度。 蚀刻室壁上的沉积物厚度的测量提供了用于量化蚀刻室的状态和状态的准确和有用的参数。 蚀刻室壁上的沉积物厚度的测量还提供了在半导体晶片被处理时随时间而不间断地测量的参数，从而在生产损失发生之前预测清洁维护的需要，但是不会中断制造处理 。