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    Microcomputer with interrupt packets
    212.
    发明公开
    Microcomputer with interrupt packets 审中-公开
    Mikrorechner mit Unterbrechungspaketen

    公开(公告)号：EP0953913A1

    公开(公告)日：1999-11-03

    申请号：EP99303255.6

    申请日：1999-04-27

    Applicant: STMicroelectronics Limited

    Inventor： Jones, Andrew Michael ,  May, Michael David

    IPC: G06F13/24

    CPC classification number: G06F13/24

    Abstract: An integrated circuit device (11) has an address and data path (15) interconnecting a CPU (12) with modules (14) the modules having event logic (8) to generate an event request packet having a destination address and the CPU decoding the packet to selectively respond to the request of the packet depending on the priority of the event.

    Abstract translation: 集成电路装置（11）具有将CPU（12）与具有事件逻辑（8）的模块（14）互连的地址和数据路径（15），以生成具有目的地地址的事件请求分组，并且CPU对 分组以根据事件的优先级选择性地响应分组的请求。

    Shared memory access
    214.
    发明公开
    Shared memory access 有权
    Zugriff zu gemeinschaftlichem Speicher

    公开(公告)号：EP0940756A1

    公开(公告)日：1999-09-08

    申请号：EP99300686.5

    申请日：1999-01-29

    Applicant: STMicroelectronics Limited

    Inventor： Rovati, Fabrizio

    IPC: G06F13/16

    CPC classification number: G06F13/1678

    Abstract: There is disclosed a method and circuit for allowing access to a shared memory by at least two controllers having different bus widths. Such method and circuit provides particular advantages in its application to controlling access to a shared memory in a digital set-top-box of a digital television receiver.
    An arbiter is provided to access between memory accesses by first and second memory access circuitry. The first memory access circuitry accesses a block of data in the shared memory, and the second memory access circuitry accesses two blocks of data in each memory access. Each second memory write access comprises reading blocks of data from first and second memory locations and then writing blocks of data to first and second memory locations.

    Abstract translation: 公开了一种用于允许具有不同总线宽度的至少两个控制器访问共享存储器的方法和电路。 这种方法和电路在其用于控制​​对数字电视接收机的数字机顶盒中的共享存储器的访问方面提供了特别的优点。 提供仲裁器以通过第一和第二存储器访问电路访问存储器访问。 第一存储器访问电路访问共享存储器中的数据块，并且第二存储器访问电路在每个存储器访问中访问两个数据块。 每个第二存储器写访问包括从第一和第二存储器位置读取数据块，然后将数据块写入第一和第二存储器位置。

    Cyclic redundancy check in a computer system
    216.
    发明公开
    Cyclic redundancy check in a computer system 有权
    在einem电脑系统中的ZüklischredundantePrüfung

    公开(公告)号：EP0936537A1

    公开(公告)日：1999-08-18

    申请号：EP99300995.0

    申请日：1999-02-11

    Applicant: STMicroelectronics Limited

    Inventor： Jones, Andrew Michael ,  Homewood, Marc Owen

    IPC: G06F9/30 ,  G06F11/10

    CPC classification number: G06F9/30018 ,  G06F11/10

    Abstract: A cyclic redundancy check value is computed by iterating a loop in which the contents of an operand (50) having a first CRC value (51) and a data value (52) are shifted 1 bit to the end at which the CRC value is located, and a generator value (55) is exclusive-ORed into corresponding respective bits of the operand only if the bit shifted out of the operand by the shift was set, and this is repeated until a data byte has been displaced entirely and a modified cyclic redundancy check value (51) occupies the most significant bytes but now incorporates the original data byte in modified form.

    Abstract translation: 通过迭代循环来计算循环冗余校验值，其中具有第一CRC值（51）和数据值（52）的操作数（50）的内容被移位1位到CRC值所在的结尾 ，并且只有当设置了从操作数移出移位位的位后，发生器值（55）才被异或运算到操作数的对应的各个位中，并重复该操作数，直到数据字节完全移位，并且修改了循环 冗余校验值（51）占用最高有效字节，但现在将原始数据字节并入修改后的形式。

    Post image techniques
    217.
    发明公开
    Post image techniques 失效
    后图像技术

    公开(公告)号：EP0901087A1

    公开(公告)日：1999-03-10

    申请号：EP98301192.5

    申请日：1998-02-18

    Applicant: STMicroelectronics Limited

    Inventor： Barrett, Geoff

    IPC: G06F17/50

    CPC classification number: G06F17/504

    Abstract: A device for synthesising a reverse model of a system comprises a first store storing bits representative of transition functions of the system, a second store storing bits representative of an estimate of transition functions of the reverse model, and processing means. The processing means comprises a logical device for transforming the transition functions of the system into constraints on the reverse model, and a parameterisation processor for applying a parameterisation of the constraints to the estimate of transition functions of reverse system to form transition functions of the reverse model.

    Abstract translation: 用于合成系统的反向模型的装置包括存储表示系统的转换功能的位的第一存储器，存储表示反向模型的转换功能的估计的位的第二存储器和处理装置。 处理装置包括用于将系统的转换功能转换为反向模型的约束的逻辑设备，以及参数化处理器，用于将约束的参数化应用于反向系统的转换函数的估计以形成反向模型的转换函数 。

    Analog-to-digital conversion in image sensors
    220.
    发明授权
    Analog-to-digital conversion in image sensors 有权
    模拟到在图像传感器数字转换

    公开(公告)号：EP2104234B1

    公开(公告)日：2011-08-31

    申请号：EP08153179.0

    申请日：2008-03-21

    Applicant: STMicroelectronics Limited

    Inventor： Purcell, Matthew ,  Storm, Graeme ,  Qu, Min

    IPC: H03M1/08 ,  H04N5/335

    CPC classification number: H04N5/3355 ,  H04N5/3575 ,  H04N5/3577 ,  H04N5/378

    Abstract: An image sensor has a per-column ADC arrangement including first and second capacitors for correlated double sampling, and a comparator circuit. The capacitors are continuously connected to, respectively, the analog pixel signal and a ramp signal without use of a hold operation. The comparator circuit comprises a differential amplifier having one input connected to the junction of the two capacitors and another input connected to a reference signal. The reference signal is preferably sampled and held from a reference voltage. The use of a differential amplifier as first stage of the comparator addresses problems arising from ground voltage bounce when a large pixel array images a scene with low contrast.

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