公开(公告)号：WO2009034926A1

公开(公告)日：2009-03-19

申请号：PCT/JP2008/066080

申请日：2008-09-05

Applicant: 国立大学法人東北大学 ,  日本ゼオン株式会社 ,  宇部興産株式会社 ,  宇部日東化成株式会社 ,  大見 忠弘 ,  藤村 誠 ,  小池 匡 ,  番場 昭典 ,  小林 章洋 ,  綿貫 耕平

Inventor： 大見 忠弘 ,  藤村 誠 ,  小池 匡 ,  番場 昭典 ,  小林 章洋 ,  綿貫 耕平

IPC: H01L21/336 ,  G02F1/1368 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3205 ,  H01L29/786

CPC classification number: H05K3/048 ,  H01L21/0331 ,  H01L27/1288 ,  H01L29/66765 ,  H05K1/0306 ,  H05K3/107 ,  H05K2201/0166 ,  H05K2201/0175

Abstract: 　本発明の課題は、超大面積の基板上に、均一に導電体層を形成した電子装置の製造方法を提供することにある。 　本発明の電子装置の製造方法においては、基板上に形成された透明樹脂膜に、ゲート電極を形成する金属膜を選択的に埋設し、ゲート電極部分には直接基板上に、一方、ゲート電極部分以外の部分には、絶縁性塗布膜上に、金属膜をスパッタリングすることにより形成され、絶縁性塗布膜上の金属膜は、絶縁性塗布膜をエッチング除去することにともなうケミカルリフトオフにより除去されている。

Abstract translation: 提供一种电子器件的制造方法，其中导体层均匀地形成在具有超大面积的基板上。 在电子设备的制造方法中，用于形成栅电极的金属膜选择性地嵌入到形成在基板上的透明树脂膜中，并且金属膜通过在栅电极部分处直接溅射在基板上而形成， 在除了栅电极部分之外的部分上的绝缘涂膜。 通过化学剥离除去绝缘涂膜上的金属膜，通过蚀刻除去绝缘涂膜。

公开(公告)号：WO2004004433A1

公开(公告)日：2004-01-08

申请号：PCT/US2003/020362

申请日：2003-06-27

Applicant: PPG INDUSTRIES OHIO, INC.

Inventor： WANG, Alan E. ,  OLSON, Kevin C.

IPC: H05K3/44

CPC classification number: H05K3/44 ,  H05K1/056 ,  H05K3/002 ,  H05K3/0052 ,  H05K3/4641 ,  H05K3/4644 ,  H05K2201/0166 ,  H05K2201/0909 ,  H05K2201/0919 ,  H05K2201/09554 ,  H05K2203/135 ,  Y10T29/49126 ,  Y10T29/49156 ,  Y10T29/49167 ,  Y10T428/12361 ,  Y10T428/24322

Abstract: Provided is a process for creating vias for a circuit assembly including the steps of (a) applying a curable coating composition to a substrate, some or all of which is electrically conductive, to form an uncured coating thereon; (b) applying a resist over the uncured coating; (c) imaging the resist in predetermined locations; (d) developing the resist to expose predetermined areas of the uncured coating; (e) removing the exposed areas of the uncured coating; and (f) heating the coated substrate of step (e) to a temperature and for a time sufficient to cure the coating. Also disclosed is a process of fabricating a circuit assembly.

Abstract translation: 提供了一种用于创建电路组件的通孔的方法，包括以下步骤：（a）将可固化涂料组合物施加到基底上，其中一些或全部导电，以在其上形成未固化的涂层; （b）在未固化的涂层上涂覆抗蚀剂; （c）在预定位置对抗蚀剂进行成像; （d）显影抗蚀剂以暴露未固化涂层的预定区域; （e）去除未固化涂层的暴露区域; 和（f）将步骤（e）的涂覆的基材加热到足以固化涂层的温度和时间。 还公开了一种制造电路组件的工艺。

公开(公告)号：WO2004004432A1

公开(公告)日：2004-01-08

申请号：PCT/US2003/020361

申请日：2003-06-27

Applicant: PPG INDUSTRIES OHIO, INC.

Inventor： WANG, Alan E. ,  OLSON, Kevin C. ,  DI STEFANO, Thomas H.

IPC: H05K3/44

CPC classification number: H05K1/0231 ,  H01L2224/16225 ,  H05K1/056 ,  H05K3/002 ,  H05K3/0052 ,  H05K3/44 ,  H05K3/4641 ,  H05K3/4644 ,  H05K2201/0166 ,  H05K2201/0397 ,  H05K2201/0909 ,  H05K2201/0919 ,  H05K2201/09309 ,  H05K2201/09554 ,  H05K2201/10446 ,  H05K2203/135 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A circuit board layer (2) in accordance with the present invention includes a conductive sheet (4) sandwiched between an insulating top layer (10) and an insulating bottom layer (14). The top and bottom layers (10) and (14) and the conductive sheet (4) define the circuit board layer (2) having an edge that includes an edge (20) of the conductive sheet (4). An insulating edge layer (18) covers substantially all of the edge (20) of the conductive sheet (4).

Abstract translation: 根据本发明的电路板层（2）包括夹在绝缘顶层（10）和绝缘底层（14）之间的导电片（4）。 顶层和底层（10）和（14）和导电片（4）限定具有包括导电片（4）的边缘（20）的边缘的电路板层（2）。 绝缘边缘层（18）几乎覆盖导电片（4）的所有边缘（20）。

公开(公告)号：WO01068752A1

公开(公告)日：2001-09-20

申请号：PCT/US2001/008684

申请日：2001-03-16

IPC: C03C25/00 ,  C03C25/10 ,  C03C25/26 ,  C03C25/28 ,  C03C25/32 ,  C03C25/42 ,  C03C25/48 ,  C08J5/08 ,  H05K1/03 ,  H05K3/00

CPC classification number: C03C25/26 ,  C03C25/00 ,  C03C25/10 ,  C03C25/28 ,  C03C25/32 ,  C03C25/42 ,  C03C25/47 ,  C03C25/48 ,  C08J5/08 ,  H05K1/0366 ,  H05K3/0047 ,  H05K2201/0166 ,  H05K2201/0175 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/0215 ,  H05K2201/0239 ,  H05K2201/0245 ,  H05K2201/0248 ,  H05K2201/0254 ,  H05K2201/029 ,  H05K2203/127 ,  Y10T428/2927 ,  Y10T428/2933 ,  Y10T428/2938 ,  Y10T428/2964 ,  Y10T442/20 ,  Y10T442/3049

Abstract: The present invention provides a fabric comprising at least one fiber strand comprising a plurality of fibers and having a resin compatible coating composition on at least a surface of the at least one fiber strand, wherein the at least one fiber strand has an Air Jet Transport Drag Force value of greater than 100,000 gram force per gram mass of strand as determined by a needle air jet nozzle unit having an internal air jet chamber having a diameter of 2 millimeters and a nozzle exit tube having a length of 20 centimeters at a strand feed rate of 274 meters per minute and an air pressure of 310 kiloPascals. The present invetion also provides a reinforced laminate comprising: (a) at least one matrix material; and (b) at least one fabric comprising at least one fiber strand comprising a plurality of fibers and having a resin compatible coating composition on at least a surface of the at least one fiber strand, wherein the at least one fiber strand has an Air Jet Transport Drag Force value of greater than 100,000 gram force per gram mass of strand as determined by a needle air jet nozzle unit having an internal air jet chamber having a diameter of 2 millimeters and a nozzle exit tube having a length of 20 centimeters at a strand feed rate of 274 meters per minute and an air pressure of 310 kiloPascals.

Abstract translation: 本发明提供了一种织物，其包含至少一根纤维束，其包含多根纤维，并且在至少一条纤维束的至少一个表面上具有树脂相容的涂料组合物，其中至少一条纤维束具有空气喷射传输拖 通过具有直径为2毫米的内部空气喷射室和具有20厘米长度的喷嘴出口管以针状进料速率的针空气喷嘴单元确定的每克质量的股线的力值大于100,000克力 每分钟274米，气压310千帕。 本发明还提供一种增强层压材料，包括：（a）至少一种基质材料; 和（b）至少一种织物，其包含至少一根包含多根纤维并且在所述至少一根纤维束的至少一个表面上具有树脂相容性涂料组合物的纤维束，其中所述至少一根纤维束具有空气喷射 通过具有直径为2毫米的内部空气喷射室的针空气喷嘴单元确定的每克质量股线的运输阻力值大于100,000克力，并且在一股线处具有长度为20厘米的喷嘴出口管 进料速度为274米/分钟，空气压力为310千帕。

公开(公告)号：WO01035704A1

公开(公告)日：2001-05-17

申请号：PCT/US2000/030015

申请日：2000-10-31

IPC: H05K1/11 ,  H05K1/00 ,  H05K1/09 ,  H05K3/00 ,  H05K3/06 ,  H05K3/38 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K3/4076 ,  H05K1/0393 ,  H05K3/002 ,  H05K3/0035 ,  H05K3/06 ,  H05K3/388 ,  H05K3/421 ,  H05K3/426 ,  H05K3/427 ,  H05K2201/0166 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09827 ,  H05K2203/0361 ,  H05K2203/0554

Abstract: The present invention provides a multi-layer double-sided wiring board which provides excellent adhesion between the conductive layer (12) and the insulating layer (10) because of the provision of an interface layer (14) therebetween, and which exhibits excellent conductivity reliability because the upper and lower conductive layers (16, 12) are joined together within the blind via (18) without interposing a dissimilar metal.

Abstract translation: 本发明提供一种多层双面布线板，由于在它们之间设置界面层（14），导电层（12）和绝缘层（10）之间具有优异的粘附性，并且其表现出优异的导电性可靠性 因为上下导电层（16,12）在盲通孔（18）内连接在一起，而不插入异种金属。

公开(公告)号：WO0109054A8

公开(公告)日：2001-04-19

申请号：PCT/US0020459

申请日：2000-07-28

Applicant: PPG IND OHIO INC

Inventor： NOVICH BRUCE E ,  LAMMON-HILINSKI KAMI ,  ROBERTSON WALTER J ,  WU XIANG ,  VELPARI VEDAGIRI ,  LAWTON ERNEST L ,  RICE WILLIAM B

IPC: C03C25/10 ,  C03C25/00 ,  C03C25/48 ,  C08J5/08 ,  D06M15/507 ,  D06M15/564 ,  D06M15/59 ,  D06M101/00 ,  H05K1/03 ,  H05K3/00

CPC classification number: C03C25/00 ,  C03C25/10 ,  C03C25/47 ,  C03C25/48 ,  C08J5/08 ,  H05K1/0366 ,  H05K3/0047 ,  H05K2201/0166 ,  H05K2201/0175 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/0239 ,  H05K2201/0245 ,  H05K2201/0254 ,  H05K2201/029 ,  H05K2203/127

Abstract: The present invention provides an at least partially coated fiber strand comprising a plurality of fibers, the coating comprising an organic component and lamellar particles having a thermal conductivity of at least 1 Watt per meter K at a temperature of 300K. The present invention also provides an at least partially coated fiber strand comprising a plurality of fibers, the coating comprising an organic component and non-hydratable, lamellar particles. The present invention further provides an at least partially coated fiber strand comprising a plurality of fibers having a resin compatible coating composition on at least a portion of a surface of at least one of said fibers, the resin compatible coating composition comprising: (a) a plurality of discrete particles formed from materials selected from non-heat expandable organic materials, inorganic polymeric materials, non-heat expandable composite materials and mixtures thereof, the particles having an average particle size sufficient to allow strand wet out; (b) at least one lubricious material different from said plurality of discrete particles; and (c) at least one film-forming material. The present invention also provides an at least partially coated fiber strand comprising a plurality of glass fibers having a resin compatible coating composition on at least a portion of a surface of at least one of said glass fibers, the resin compatible coating composition comprising: (a) a plurality of lamellar, inorganic particles having a Mohs' hardness value which does not exceed the Mohs' hardness value of said glass fibers; and (b) at least one polymeric material. The present invention further provides an at least partially coated fiber strand comprising a plurality of glass fibers having a resin compatible coating composition on at least a portion of a surface of at least one of said glass fibers, the resin compatible coating composition comprising: (a) a plurality of hollow, non-heat expandable organic particles; and (b) at least one lubricious material different from the at least one hollow organic particle.

公开(公告)号：WO00067536A1

公开(公告)日：2000-11-09

申请号：PCT/US1999/018660

申请日：1999-08-17

IPC: G03F7/40 ,  H01L21/311 ,  H05K3/00 ,  H05K3/06

CPC classification number: H01L21/31133 ,  H05K3/002 ,  H05K2201/0145 ,  H05K2201/0154 ,  H05K2201/0166 ,  H05K2203/0793

Abstract: A process for making flexible circuits wherein the etching of a polymeric film is accomplished by dissolving portions thereof with concentrated aqueous base using a UV-curable 100 % active liquid photoresist as a mask, comprising the steps of laminating the resist on a polymeric film, exposing a pattern into the resist, developing the resist with a dilute aqueous solution until desired image is obtained, etching portions of the polymeric film not covered by the crosslinked resist with a concentrated base at a temperature of from 50 DEG C to 120 DEG C, and then stripping the resist off the polymeric film.

Abstract translation: 一种用于制造柔性电路的方法，其中通过使用可UV固化的100％活性液体光致抗蚀剂作为掩模将其部分用浓缩的水性碱溶解，从而实现聚合物膜的蚀刻，其包括以下步骤：将抗蚀剂层压在聚合物膜上， 形成抗蚀剂的图案，用稀释的水溶液显影抗蚀剂，直到获得所需的图像，在50℃至120℃的温度下，用浓缩碱蚀刻未被交联抗蚀剂覆盖的聚合物膜的部分蚀刻部分，以及 然后将抗蚀剂剥离聚合物膜。

公开(公告)号：WO00021900A1

公开(公告)日：2000-04-20

申请号：PCT/US1999/021443

申请日：1999-10-08

IPC: C03C25/10 ,  C08J5/08 ,  D03D1/00 ,  D03D15/12 ,  D06M11/00 ,  D06M11/80 ,  D06M15/507 ,  D06M101/00 ,  H05K1/03 ,  H05K3/00

CPC classification number: C08J5/08 ,  C03C25/47 ,  H05K1/0366 ,  H05K3/0047 ,  H05K2201/0166 ,  H05K2201/0175 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/0239 ,  H05K2201/0245 ,  H05K2201/0254 ,  H05K2201/029 ,  H05K2203/127

Abstract: One aspect of the present invention is a prepreg for an electronic support, the prepreg comprising: (a) a polymeric matrix material; and (b) a fabric comprising a strand comprising glass fibers, at least a portion of the fabric having a coating which is compatible with the polymeric matrix material, the prepreg having a drill tip percent wear of no greater than about 32 percent, as determined after drilling 2000 holes through a stack of 3 laminates, each laminate including eight of the prepregs, at a hole density of 62 holes per square centimeter (400 holes per square inch) and a chip load of 0.001 with a 0.46 mm (0.018 inch) diameter tungsten carbide drill. The present invention also provides a laminate incorporating the prepreg. Another aspect of the present invention is a prepreg for an electronic support, the prepreg comprising: (a) a polymeric matrix material; and (b) a woven reinforcement fabric comprising glass fibers, at least a portion of the fabric having a coating which is compatible with the polymeric matrix material, the prepreg having a deviation distance of no greater than about 36 micrometers, as determined after drilling 2000 holes through a stack of 3 laminates at a hole density of 62 holes per square centimeter (400 holes per square inch) and a chip load of 0.001 with a 0.46 mm (0.018 inch) diameter tungsten carbide drill. The present invention also provides a laminate incorporating the prepreg.

Abstract translation: 本发明的一个方面是用于电子载体的预浸料坯，所述预浸料包括：（a）聚合物基质材料; 和（b）包含包含玻璃纤维的股线的织物，所述织物的至少一部分具有与所述聚合物基质材料相容的涂层，所述预浸料坯具有不大于约32％的钻头百分比磨损，如所确定的 在通过3个层压体的堆叠中钻孔2000个孔之后，每个层压体包括八个预浸料坯，孔密度为每平方厘米62个孔（400个孔/平方英寸），并且具有0.46mm（0.018英寸）的0.001的切屑负载） 直径碳化钨钻头。 本发明还提供了包含预浸料的层压体。 本发明的另一方面是一种用于电子载体的预浸料，所述预浸料包括：（a）聚合物基质材料; 和（b）包含玻璃纤维的织造增强织物，所述织物的至少一部分具有与所述聚合物基质材料相容的涂层，所述预浸料坯具有不大于约36微米的偏差距离，如在钻井2000之后测定的 孔通过堆叠的3个层压板，孔密度为每平方厘米62孔（400个孔/平方英寸），芯片负载为0.001，直径为0.46毫米（0.018英寸）的碳化钨钻头。 本发明还提供了包含预浸料的层压体。

公开(公告)号：WO1992015408A1

公开(公告)日：1992-09-17

申请号：PCT/CH1992000035

申请日：1992-02-21

Applicant: DYCONEX PATENTE AG HEINZE & CO ,  SCHMIDT, Walter ,  MARTINELLI, Marco ,  FREI, Alexandra

Inventor： DYCONEX PATENTE AG HEINZE & CO

IPC: B07B01/46

CPC classification number: B07B1/4618 ,  B01D39/1692 ,  B01D67/0034 ,  B01D69/12 ,  B01D2323/345 ,  B07B1/4663 ,  G02B6/122 ,  G02B6/4228 ,  G02B6/423 ,  H05K1/0272 ,  H05K1/0393 ,  H05K3/0041 ,  H05K3/42 ,  H05K2201/0166 ,  H05K2201/0394 ,  H05K2201/064 ,  H05K2201/09509 ,  H05K2203/0554

Abstract: In order to produce a specific microsieve having a large number of precisely arranged passages of whatever form, a plastic foil (1) is coated with a layer of etch-resistant material (2, 2'). Recesses (4, 4') are etched in this layer (2, 2') at the locations where passages are to be formed. In a further process step, the passages (5) are produced by a plasma etching process. In addition, ducts (K, L) are inserted into the coating layer (2, 2') either as channels (K) or as solid paths. Several microsieves (S1, S2) are superimposed to form a specific composite body, oriented in such a way that the ducts (5, K, L) are cross-linked in the x, y and z directions. Examples of applications are fluid-conducting diaphragms, electroconductive multilayers and cross-linked light-guide microsystems.

Abstract translation: 为了生产具有任何形式的大量精确布置的通道的特定微量筛，塑料箔（1）涂覆有一层抗蚀材料（2,2'）。 在要形成通道的位置，在该层（2,2'）中蚀刻凹槽（4,4'）。 在另外的工艺步骤中，通过等离子体蚀刻工艺制造通道（5）。 此外，管道（K，L）作为通道（K）或固体路径插入到涂层（2,2'）中。 叠加几个微通道（S1，S2）以形成一个特定的复合体，以使得管道（5，K，L）在x，y和z方向上交联的方式定向。 应用实例是导流隔膜，导电多层和交联光导微系统。

公开(公告)号：WO1991003375A1

公开(公告)日：1991-03-21

申请号：PCT/US1990004761

申请日：1990-08-24

Applicant: DAVID SARNOFF RESEARCH CENTER, INC.

Inventor： DAVID SARNOFF RESEARCH CENTER, INC. ,  CONLON, Edward, J. ,  BOARDMAN, Simon, M. ,  PRABHU, Ashok, N. ,  PENDRICK, Valerie, Ann

IPC: B32B09/00

CPC classification number: H05K3/4061 ,  H05K1/0306 ,  H05K1/092 ,  H05K3/002 ,  H05K3/0041 ,  H05K3/4644 ,  H05K3/4667 ,  H05K2201/0166 ,  H05K2203/0384 ,  H05K2203/0582 ,  H05K2203/308

Abstract: In the manufacture of printed circuit boards, a first photoresist post (14) is patterned on the substrate where via holes are to be made. A dielectric layer (16) is put down, a second photoresist layer (18) patterned so as to have openings over and in alignment with the photoresist posts (14), and the dielectric removed from the via holes. Barrier layers to reduce interaction between layers of copper, dielectric and photoresist during filling of the via holes with a conductor via fill ink are also described.

Abstract translation: 在印刷电路板的制造中，在要制造通孔的基板上图案化第一光致抗蚀剂柱（14）。 介电层（16）被放下，第二光致抗蚀剂层（18）被图案化以具有在光致抗蚀剂柱（14）上方并且与光致抗蚀剂柱（14）对准的开口，并且电介质从通孔去除。 还描述了阻挡层，以减少在用导体通过填充油墨填充通孔期间铜，电介质和光致抗蚀剂层之间的相互作用。