公开(公告)号：GB2404266B

公开(公告)日：2007-08-22

申请号：GB0415567

申请日：2004-07-12

Applicant: SAMSUNG ELECTRONICS CO LTD

Inventor： KIM MIN-SU

IPC: G06F12/00 ,  G06F12/10 ,  G06F9/46 ,  G06F9/50 ,  G06F12/1036

Abstract: A method and apparatus for data processing including a microprocessor for simultaneously processing a plurality of processes, where a process memory is assigned to one or more processes, the processes include corresponding threads of that are assigned to corresponding thread memories that are independent from the process memory, and have access to the process memory.

公开(公告)号：GB0623276D0

公开(公告)日：2007-01-03

申请号：GB0623276

申请日：2006-11-22

Applicant: TRANSITIVE LTD

IPC: G06F12/0815 ,  G06F12/1036 ,  G06F12/109

Abstract: A method and apparatus to protect memory consistency in a multiprocessor computing system are described, in particular relating to program code conversion such as dynamic binary translation. The exemplary system provides a memory, processors and a controller/translator unit (CTU) arranged to convert subject code into at least first and second target code portions executable on the processors. The CTU comprises an address space allocation unit to provide virtual address space regions and direct the target code portions to access the memory therethough; a shared memory detection unit to detect a request to access a shared memory area, accessible by both target code portions, and to identify at least one group of instructions in the first target code portion which access the shared memory area; and a memory protection unit to selectively apply memory consistency protection in relation to accesses to the shared memory area by the identified group of instructions.

公开(公告)号：GB2404266A

公开(公告)日：2005-01-26

申请号：GB0415567

申请日：2004-07-12

Applicant: SAMSUNG ELECTRONICS CO LTD

Inventor： KIM MIN-SU

IPC: G06F12/00 ,  G06F9/50 ,  G06F12/10 ,  G06F12/1036 ,  G06F9/46 ,  G06F9/38

Abstract: A system for simultaneously processing processes where a process has one or more threads includes a process memory assigned to the processes and one or more thread memories, each thread memory corresponding to a thread. The thread memories are independent from the process memory. The process memory is used by the threads but the threads cannot access other thread memories. A translation lookaside buffer (TLB) includes a tag unit which includes a thread ID and a virtual page number which are used to translate a virtual address to a physical address. The tag unit also includes a process ID and a thread bit which determines whether the virtual address is an address for a process memory or a thread memory.

公开(公告)号：FR2812956A1

公开(公告)日：2002-02-15

申请号：FR0010550

申请日：2000-08-10

Applicant: GEMPLUS CARD INT

Inventor： GARNIER THIERRY

IPC: G06F12/1036 ,  G06F12/02 ,  G06F12/08

公开(公告)号：DE4234194A1

公开(公告)日：1993-04-22

申请号：DE4234194

申请日：1992-10-10

Applicant: INTEL CORP

Inventor： HAMMOND GARY N ,  DUBEY PRADEEP

IPC: G06F12/02 ,  G06F12/08 ,  G06F12/0875 ,  G06F12/10 ,  G06F12/1036 ,  G06F12/12

公开(公告)号：CA1308202C

公开(公告)日：1992-09-29

申请号：CA584970

申请日：1988-12-05

Applicant: IBM

Inventor： BAUM RICHARD I ,  BORDEN TERRY L ,  BUTWELL JUSTIN R ,  CLARK CARL E ,  GANEK ALAN G ,  LUM JAMES ,  MALL MICHAEL G ,  PLAMBECK KENNETH E ,  SCALZI CASPER A ,  SCHMALZ RICHARD J ,  SMITH RONALD M ,  THOMAS JULIAN

IPC: G06F12/08 ,  G06F9/46 ,  G06F12/02 ,  G06F12/10 ,  G06F12/1036 ,  G06F12/14

Abstract: PO98/-004 ACCESS REGISTER TRANSLATION MEANS FOR ADDRESS GENERATING MECHANISM FOR MULTIPLE VIRTUAL SPACES A method and apparatus is provided to translate the contents of access registers into information for use in performing addressing functions for multiple virtual address spaces. The access registers represent the full addressing capability of the system but do not directly contain the addressing information. The system has a plurality of general purpose registers, a plurality of access registers associated with the general registers, an access list having access list entries which is addressed by the contents of the access register, memory storage for holding address space number second table entries (ASTE), where the contents of the access list entry locate the ASTE and where the ASTE contains the addressing information needed to translate a virtual address when combined with the contents of a general purpose register. Access register translation (ART) consists of the process of determining addressing information by using the access list entry and the ASTE. The results of the ART process are stored in an ART lookaside buffer (ALB) which stores the results of ART while valid for later use.

公开(公告)号：DE4019961A1

公开(公告)日：1991-01-10

申请号：DE4019961

申请日：1990-06-22

Applicant: HITACHI LTD ,  HITACHI COMPUTER ENG

Inventor： KAWAMURA TOSHIAKI ,  SHIMURA NOBUYUKI ,  TAMANO AKIHIRO ,  ABE SHUICHI ,  FUKAGAWA MASAKAZU ,  YAMAMOTO MICHITAKA ,  ONITSUKA TAKAHIRO

IPC: G06F12/10 ,  G06F12/1036

Abstract: An instruction decoder (1) provides a displacement Values (DP), an index register number (IX) and a base register number (BR). The latter are entered into a general register (2) and are summed (3) with the displacement valve. A block of access registers has 16 locations that define initial address spaces. An addresse conversion stage (5) receives the logical address valve (20) and provides an obsolute address value (22). The address values are combined in a table (6) having logic address (LA), operator (STO), validity field (V) and absolute address (AA),. The unit combines with a stage (11) that modifies part of the address. ADVANTAGE - Improves conversion of virtual addresses into absolute addresses.

公开(公告)号：CA1270064C

公开(公告)日：1990-06-05

申请号：CA511838

申请日：1986-06-18

IPC: G06F9/42 ,  G06F9/44 ,  G06F12/08 ,  G06F12/084 ,  G06F12/0846 ,  G06F12/10 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/109 ,  G06F13/16 ,  G06F13/40

公开(公告)号：FR2423006B1

公开(公告)日：1988-06-10

申请号：FR7908959

申请日：1979-04-09

Applicant: PHILIPS NV

IPC: G06F9/22 ,  F25D1/00 ,  G06F1/18 ,  G06F1/20 ,  G06F9/26 ,  G06F12/10 ,  G06F12/1036 ,  H05K7/14 ,  H05K7/20 ,  G06F15/00

公开(公告)号：DE3312391C2

公开(公告)日：1987-04-02

申请号：DE3312391

申请日：1983-04-06

Applicant: SIEMENS AG, 1000 BERLIN UND 8000 MUENCHEN, DE

Inventor： BRAEUER, GERALD, 8000 MUENCHEN, DE

IPC: G06F12/08 ,  G06F12/1036 ,  G11C15/00 ,  G11C15/04 ,  G11C7/00