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    SPLIT INSTRUCTION PAGING METHOD AND MEANS
    1.
    发明专利
    SPLIT INSTRUCTION PAGING METHOD AND MEANS 未知

    公开(公告)号：CA2062135A1

    公开(公告)日：1992-11-24

    申请号：CA2062135

    申请日：1992-03-02

    Applicant: IBM

    Inventor： MCCAULEY DONALD W ,  SCHMALZ RICHARD J ,  SMITH RONALD M SR ,  STILLMAN SUSAN B

    IPC: G06F13/42 ,  G06F12/02 ,  G06F13/16 ,  G06F15/17 ,  G06F13/14

    Abstract: PO9-90-032 SPLIT INSTRUCTION PAGING METHOD AND MEANS Asynchronously transfers blocks of data (called pages) between two different electronic media of a data processing system. The different media may be a system main storage and a system expanded storage or a non-volatile external type of storage, either of which use different addressing than the main storage. All of these storages may be made of DRAM or SRAM technology with battery backup when necessary. The invention splits the involvement of a program requesting a page transfer into a pair of instructions per page transfer executing on one or more central processors. The first instruction of a pair starts another processor that controls the asynchronous page transfer, and the second instruction of the pair enables the communication of the end of the page transfer to the program. Neither instruction in the pair interrupts the program for the page transfer. A processor executing the starting instruction is immediately free to execute any other available instructions. Although both instructions in a pair may be executed by one processor, the pair may be executed by separate processors. And the execution of other instructions may overlap the page transfer between the execution of the pair.

    PROCESS USING VIRTUAL ADDRESSING IN A NON-PRIVILEGED INSTRUCTION TO CONTROL THE COPYING OF A PAGE OF DATA IN OR BETWEEN MULTIPLE MEDIA
    2.
    发明专利
    PROCESS USING VIRTUAL ADDRESSING IN A NON-PRIVILEGED INSTRUCTION TO CONTROL THE COPYING OF A PAGE OF DATA IN OR BETWEEN MULTIPLE MEDIA 未知

    公开(公告)号：CA2024444C

    公开(公告)日：1995-08-15

    申请号：CA2024444

    申请日：1990-08-31

    Applicant: IBM

    Inventor： BLANDY GEOFFREY O ,  EMMES DAVID B ,  HILL RONALD F ,  LINDQUIST DAVID B ,  PLAMBECK KENNETH E ,  SCALZI CASPER A ,  SCHMALZ RICHARD J

    IPC: G06F12/10 ,  G06F12/14 ,  G06F12/00

    Abstract: A single non-privileged instruction copies a page of data from a source virtual address to a destination virtual address, regardless of which of plural electronic storage media contain the page locations, and without the intervention of any supervisory program when media and virtual addressing have been previously determined for the locations of the subject pages. The instruction is not required to specify which of the plural media it will use, does not require its user to know what backing media it will access, does not require main storage (MS) to be one of its backing media, and allows different types of physical addressing to be used by the different backing media. The instruction can lock any page for use in an MP. No physical direction of data movement is provided within the non-privileged machine instruction, which only designates virtual direction of movement. The separation of virtual direction from physical direction is done by avoiding instruction control over selection of electronic media. The non-privileged instruction can nevertheless express a preference for obtaining a copy of the destination page in an electronic medium in which the content of the page can be processed by further instructions. Also, the instruction can cause invocation of a privileged control program to avoid the need for a following condition code test instruction. A privileged instruction is also provided to wait for the completion of the unprivileged instruction and to invalidate a non-MS medium page whether it is unlocked or locked, either correctly or incorrectly.

    NONHIERARCHICAL PROGRAM AUTHORIZATION MECHANISM
    4.
    发明专利
    NONHIERARCHICAL PROGRAM AUTHORIZATION MECHANISM 未知

    公开(公告)号：CA1313424C

    公开(公告)日：1993-02-02

    申请号：CA587711

    申请日：1989-01-06

    Applicant: IBM

    Inventor： BAUM RICHARD I ,  BORDEN TERRY L ,  BUTWELL JUSTIN R ,  CLARK CARL E ,  GANEK ALAN G ,  LUM JAMES ,  MALL MICHAEL G ,  PAGE DAVID R ,  PLAMBECK KENNETH E ,  SCALZI CASPER A ,  SCHMALZ RICHARD J

    IPC: G06F12/08 ,  G06F9/46 ,  G06F12/10 ,  G06F12/14 ,  G06F21/24

    Abstract: PO9-87-006 NONHIERARCHICAL PROGRAM AUTHORIZATION MECHANISM A program authorization mechanism for authorizing access to an address space in the main memory of a computer system by a program being run under a multiple address space facility. An access-list entry is associated with each address space, each access-list entry being designated by an access list-entry token contained in an access register. Each access-list entry includes a private indicator which indicates if the associated address space can be accessed by all programs from this access-list entry or if the associated address space can only be accessed by an authorized program. For a program to be authorized, an extended authorization index in a control register must match an access-list extended authorization index in the access-list entry, or the extended authorization index value must be authorized in an authority table associated with the address space. An instruction for testing a given extended authorization index for a given access-list-entry is also disclosed.

    ADDRESS GENERATING MECHANISM FOR MULTIPLE VIRTUAL SPACES
    7.
    发明专利
    ADDRESS GENERATING MECHANISM FOR MULTIPLE VIRTUAL SPACES 未知

    公开(公告)号：CA1153824A

    公开(公告)日：1983-09-13

    申请号：CA368423

    申请日：1981-01-13

    Applicant: IBM

    Inventor： BUTWELL JUSTIN R ,  SCALZI CASPER A ,  SCHMALZ RICHARD J

    IPC: G06F9/34 ,  G06F12/06 ,  G06F12/10 ,  G06F12/14 ,  G06F13/00

    Abstract: PO9-79-012 The detailed embodiment associates access registers (AR's) with the general purpose registers (GPR's) in a data processor. The AR's are each loaded with a unique STD (segment table descriptor). The STD comprises a segment table address in main storage and a segment table length field. There are 15 AR's associated respectively with 15 GPR's in a processor to define a subset of up to 15 data address spaces. The STD in an AR is selected for address translation when the associated GPR is selected as a storage operand base register, such as being the GPR selected by the B-field in an IBM System/370 instruction. The invention allows each AR to specify that it does not use the STD in its associated AR to define its data address space, but instead uses the STD in the program address space AR. However, the STD content of an AR is not selected for an address translation if the associated GPR is selected for a purpose other than as a storage operand base register, such as if a GPR is selected as an index (X) register or as a data source or sink register (R) for an instruction. A sixteenth AR may be provided to define and control the executing program address space, which may also contain data. The embodiment obtains authority and other control for access to and use of the content in each address space by also associating an AR Control Vector (ARCV) register with each AR.

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