公开(公告)号：EP2019572A2

公开(公告)日：2009-01-28

申请号：EP08013359.8

申请日：2008-07-24

Applicant: TDK Corporation

Inventor： Kanemaru, Yoshikazu ,  Kawabata, Kenichi

IPC: H05K3/00 ,  H01L23/538

CPC classification number: H05K3/0052 ,  H01L23/49838 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K1/112 ,  H05K1/185 ,  H05K3/0097 ,  H05K3/4602 ,  H05K2201/09136 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2201/2009 ,  H05K2203/0169 ,  H05K2203/1469 ,  Y02P70/611 ,  Y10T29/49124 ,  H01L2224/82 ,  H01L2924/00

Abstract: The object of the present invention is to provide an assembly substrate which is easily handled and capable of suppressing occurrence of warpage, and offers high productivity and economic efficiency, and its manufacturing method. A work board 100 includes an insulating layer 21 on one surface of a substantially rectangular-shaped substrate 11, and electronic components 41 and a plate-like integrated frame 51 are embedded inside the insulating layer 21. The plate-like integrated frame 51 has a plurality of concave portions 53 arranged in parallel at its inner periphery wall 52a, and arranged on a non-placing area of the electronic components 41 so as to surround a plurality of the electronic components 41 (groups).

公开(公告)号：US12068219B2

公开(公告)日：2024-08-20

申请号：US17793712

申请日：2021-02-19

Applicant: MITSUBISHI MATERIALS CORPORATION

Inventor： Toyo Ohashi ,  Yoshiaki Sakaniwa

IPC: H05K1/02 ,  H01L23/373 ,  H05K7/20

CPC classification number: H01L23/3735 ,  H01L23/3736 ,  H05K1/0204 ,  H05K1/0271 ,  H05K7/205 ,  H05K7/20509 ,  H05K2201/068 ,  H05K2201/09136

Abstract: A heat sink integrated insulating circuit substrate includes: a heat sink including a top plate part and a cooling fin; an insulating resin layer formed on the top plate part of the heat sink; and a circuit layer made of metal pieces arranged on a surface of the insulating resin layer opposite to the heat sink, wherein, when a maximum length of the top plate part is defined as L, an amount of warpage of the top plate part is defined as Z, and deformation of protruding toward a bonding surface side of the top plate part of the heat sink is defined as a positive amount of warpage, and a curvature of the heat sink is defined as C=|(8×Z)/L2|, a ratio P/Cmax between a maximum curvature Cmax(I/m) of the heat sink during heating from 25° C. to 300° C. and peel strength P (N/cm) of the insulating resin layer satisfies P/Cmax>60.

公开(公告)号：US11997801B2

公开(公告)日：2024-05-28

申请号：US17741388

申请日：2022-05-10

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Woo Seok Yang ,  Jae Han Park ,  Jung Hyun Cho

IPC: H05K3/46 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K3/4697 ,  H05K1/115 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/0209 ,  H05K2201/09136

Abstract: A printed circuit board includes: a core portion including a cavity in one surface thereof; first and second penetration holes disposed in a bottom surface of the cavity and penetrating through the core portion; an electronic component disposed in the cavity; and an insulating material filling the cavity and each of the first and second penetration holes, wherein a sidewall of the cavity is higher than the electronic component.

公开(公告)号：US20230422403A1

公开(公告)日：2023-12-28

申请号：US17851097

申请日：2022-06-28

Applicant: Taiwan Semiconductor Manufacturing Company

Inventor： Hsien-Wen Liu ,  Shih-Ting Hung ,  Jyun-Lin Wu ,  Yao-Chun Chuang ,  Yinlung Lu

IPC: H05K3/22 ,  H05K3/34 ,  H05K1/18 ,  B23K1/00

CPC classification number: H05K3/225 ,  H05K3/341 ,  H05K1/181 ,  B23K1/0016 ,  H05K2201/09136 ,  B23K2101/42

Abstract: Methods for improving joinder between a surface-mount package and a printed circuit board are disclosed. The warpage at a corner of the surface-mount package and at a corresponding corner of a joint area on the printed circuit board are measured to determine the degree of mismatch. A mini-pad is applied to the corner between the surface-mount package and the joint area on the printed circuit board. The thickness of the mini-pad pushes against the surface-mount package and the printed circuit board, reducing the degree of mismatch below a critical dimension of a ball grid array of the surface-mount package. The surface-mount package can then be soldered to the joint area, reducing or preventing the formation of solder bridges and short circuits.

公开(公告)号：US20180076186A1

公开(公告)日：2018-03-15

申请号：US15822039

申请日：2017-11-24

Applicant: Toshiba Memory Corporation

Inventor： Hayato MASUBUCHI ,  Naoki Kimura ,  Manabu Matsumoto ,  Toyota Morimoto

IPC: H01L25/18 ,  H05K1/02 ,  H05K3/30 ,  H01L23/528 ,  H01L23/498 ,  H01L25/00 ,  H01L27/115

CPC classification number: H01L25/18 ,  G11C5/02 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5286 ,  H01L23/552 ,  H01L23/562 ,  H01L25/0655 ,  H01L25/50 ,  H01L27/115 ,  H01L2924/0002 ,  H05K1/0225 ,  H05K1/0271 ,  H05K1/0298 ,  H05K1/181 ,  H05K3/305 ,  H05K2201/09136 ,  H05K2201/09681 ,  H05K2201/10159 ,  Y02P70/613 ,  H01L2924/00

Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.

公开(公告)号：US09867284B2

公开(公告)日：2018-01-09

申请号：US15501829

申请日：2015-08-04

Applicant: AT & S Austria Technologie & Systemtechnik Aktiengesellschaft

Inventor： Elisabeth Kreutzwiesner ,  Gernot Schulz

IPC: H05K1/03 ,  H05K1/02 ,  H05K3/46 ,  H05K3/14 ,  H05K3/16 ,  H05K3/12

CPC classification number: H05K1/0271 ,  H05K1/0207 ,  H05K3/12 ,  H05K3/146 ,  H05K3/16 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4688 ,  H05K2201/0195 ,  H05K2201/0323 ,  H05K2201/068 ,  H05K2201/09136

Abstract: A mounting device for mounting electronic components, wherein the mounting device comprises an electrically conductive structure having a first value of thermal expansion in at least one pre-defined spatial direction, an electrically insulating structure having a second value of thermal expansion in the at least one pre-defined spatial direction being different from the first value and being arranged on the electrically conductive structure, and a thermal expansion adjustment structure having a third value of thermal expansion in the at least one pre-defined spatial direction, wherein the third value is selected and the thermal expansion adjustment structure is located so that thermally induced warpage of the mounting device resulting from a difference between the first value and the second value is at least partially compensated by the thermal expansion adjustment structure.

公开(公告)号：US09832860B2

公开(公告)日：2017-11-28

申请号：US14498958

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Robert Starkston ,  John Guzek ,  Patrick Nardi ,  Keith Jones ,  Javier Soto Gonzalez

IPC: H05K1/02 ,  H01L23/00 ,  H01L23/16 ,  H01L23/498 ,  H05K3/00 ,  H05K3/28

CPC classification number: H05K1/0271 ,  H01L23/16 ,  H01L23/49833 ,  H01L23/562 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K3/0052 ,  H05K3/0097 ,  H05K3/284 ,  H05K2201/09136 ,  H05K2201/10977 ,  H05K2201/2009

Abstract: Techniques are disclosed for forming a package substrate with integrated stiffener. A panel of package substrates are provided. An adhesion layer is then formed on each package substrate of the panel of package substrates. A panel of stiffeners are then attached to the panel of package substrates by the adhesion layer, each stiffener corresponding to a respective package substrate. The panel of package substrates is then singulated into individual package substrates with integrated stiffeners. The stiffeners on the singulated package substrates include tabs that extend to the edges of the package substrates.

公开(公告)号：US09826646B2

公开(公告)日：2017-11-21

申请号：US14721247

申请日：2015-05-26

Applicant: FUJIKURA LTD.

Inventor： Koji Munakata

IPC: H05K1/02 ,  H05K3/46 ,  H05K1/18 ,  H01L25/065 ,  H01L23/538

CPC classification number: H05K3/4614 ,  H01L23/5389 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2924/3511 ,  H05K1/186 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/09136 ,  H05K2201/096 ,  Y10T156/10

Abstract: A component built-in board comprises a multi-layer structure comprising a plurality of unit boards stacked therein a plurality of electronic components built in thereto in a stacking direction. The plurality of unit boards include: a first board having a first insulating layer and comprising an opening in which the electronic component is housed; and an intermediate board adjacent to the first board and comprising a first adhesive layer provided on at least a side of the first board of a second insulating layer. The intermediate board includes a first wiring layer formed at a position overlapping in the stacking direction a gap between an inner periphery of the opening and an outer periphery of the electronic component of the first board on a surface on the first board side of the second insulating layer.

公开(公告)号：US09754632B2

公开(公告)日：2017-09-05

申请号：US15254825

申请日：2016-09-01

Applicant: Toshiba Memory Corporation

Inventor： Hayato Masubuchi ,  Naoki Kimura ,  Manabu Matsumoto ,  Toyota Morimoto

IPC: G11C5/02 ,  H05K3/30 ,  H01L23/498 ,  H01L27/115 ,  H01L23/552 ,  H01L23/00 ,  H01L25/065 ,  H05K1/18 ,  H01L23/31 ,  H05K1/02

CPC classification number: H01L25/18 ,  G11C5/02 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5286 ,  H01L23/552 ,  H01L23/562 ,  H01L25/0655 ,  H01L25/50 ,  H01L27/115 ,  H01L2924/0002 ,  H05K1/0225 ,  H05K1/0271 ,  H05K1/0298 ,  H05K1/181 ,  H05K3/305 ,  H05K2201/09136 ,  H05K2201/09681 ,  H05K2201/10159 ,  Y02P70/613 ,  H01L2924/00

Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.

公开(公告)号：US20170238409A1

公开(公告)日：2017-08-17

申请号：US15501821

申请日：2015-06-12

Applicant: TANAZAWA HAKKOSHA CO., LTD.

Inventor： Keiichiro YAMAMOTO ,  Kazuhiro SASAMOTO

IPC: H05K1/02 ,  H05K3/06 ,  H05K3/46

CPC classification number: H05K1/0203 ,  H05K1/0209 ,  H05K1/0271 ,  H05K3/06 ,  H05K3/064 ,  H05K3/067 ,  H05K3/26 ,  H05K3/3452 ,  H05K3/4644 ,  H05K2201/068 ,  H05K2201/09136 ,  H05K2203/0577

Abstract: The object of the present invention is to provide a printed circuit board that improves the heat radiating effect as the entire printed circuit board and a manufacturing method for such a printed circuit board. A printed circuit board includes a base member having two main surfaces, at least one heat-radiating conductor layer formed on at least one of the main surfaces of the two main surfaces of the base member and a solder resist layer formed on a surface of the heat-radiating conductor layer, and in this printed circuit board, the heat-radiating conductor layer has two main surfaces and at least one side face, the heat-radiating conductor layer has its one main surface of the two main surfaces made in planar contact with the main surface of the base member, the solder resist layer further has an etching liquid resistance, and is formed on the other main surface of the two main surfaces of the heat-radiating conductor layer, with the side face of the heat-radiating conductor layer being exposed, and the heat-radiating conductor layer and the solder resist layer are allowed to form a laminate 24 having a substantially convex shape with an appropriate height.