公开(公告)号：EP2785633A1

公开(公告)日：2014-10-08

申请号：EP12794949.3

申请日：2012-11-29

Applicant: Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Inventor： CASSET, Fabrice

IPC: B81B3/00 ,  F03G7/06 ,  H01L41/113 ,  H02N10/00 ,  H02N2/00 ,  H03H9/15 ,  F24J3/00 ,  H03H9/24

CPC classification number: F24V99/00 ,  B81B3/0024 ,  B81B3/0081 ,  B81B2201/0271 ,  B81B2201/031 ,  B81B2201/032 ,  F03G7/06 ,  H01L41/1136 ,  H02N2/18

Abstract: The invention relates to a device for generating a second temperature variation ΔΤ
2 from a first use temperature variation ΔΤ
1 , comprising an elastocaloric material layer (30), the internal temperature of which is capable of varying from ΔΤ
2 in response to a given variation Δσ in a mechanical stress applied onto said elastocaloric material layer, the given variation Δσ being induced by the first temperature variation ΔΤ
1 , and a suspended element (24) in mechanical contact with the elastocaloric material layer such as to apply, onto said layer, a mechanical stress that varies in response to the use temperature variation ΔΤ
1 . Said suspended element (24) is set up such as to cause variation, from Δσ, in the mechanical stress applied onto the elastocaloric material layer in response to the temperature variation ΔΤ
1 such as to thereby generate the second temperature variation ΔΤ
2 .

公开(公告)号：EP2728904A1

公开(公告)日：2014-05-07

申请号：EP12803575.5

申请日：2012-06-26

Applicant: Ingen MSL Inc.

Inventor： Lee Seung-Mok

IPC: H04R19/00 ,  H01L29/84 ,  H04R31/00

CPC classification number: H02N1/00 ,  B06B1/0292 ,  B81B2201/0271 ,  B81B2207/015 ,  B81C1/00246 ,  B81C2203/031 ,  B81C2203/075 ,  G01H11/06 ,  G01N29/2406 ,  H01L29/84

Abstract: To provide a transducer, and a method for manufacturing the transducer, the transducer which comprises a substrate-side electrode provided in one side of an insulative substrate and an opposite plate including an opposite electrode disposed opposite to the substrate-side electrode, and which performs a function such as reduction in impedance, conversion of capacitance, signal amplification, thereby achieving size reduction of the transducer itself.
[Means for Solution]
An upper plate 1 made of silicon monocrystal is arranged so as to face a substrate-side electrode 2. In the upper plate 1, an integrated circuit section 5 which is an impurity region of an IC circuit is formed by a thermal diffusion method or ion implantation method, for example. By the transducer 10, improvement in conversion efficiency, improvement in productivity, and size reduction of a mount system are achieved.

Abstract translation: 为了提供换能器及其制造方法，所述换能器包括设置在绝缘基板的一侧的基板侧电极和相对的基板侧电极，所述相对的基板侧电极与所述基板侧电极相对设置， 诸如减小阻抗，电容转换，信号放大等功能，从而实现换能器本身的尺寸减小。 [解决方案]由单晶硅制成的上板1以与基板侧电极2相对的方式配置。在上板1中，作为IC电路的杂质区域的集成电路部5由 热扩散法或离子注入法。 通过换能器10，实现了转换效率的提高，生产率的提高和安装系统的尺寸减小。

公开(公告)号：EP2676923A1

公开(公告)日：2013-12-25

申请号：EP12172788.7

申请日：2012-06-20

Applicant: IMEC

Inventor： Severi, Simone ,  Verbist, Agnes

IPC: B81C1/00

CPC classification number: B81C1/00246 ,  B81B2201/0271 ,  B81B2207/015 ,  B81B2207/03 ,  B81C2203/0771 ,  G05D23/1928 ,  G05D23/20 ,  G05D23/24 ,  H03H3/0073 ,  H03H3/0076

Abstract: The invention is related to a method for producing parallel conductive lines on the surface of a MEMS device. In the method of the invention, a first conductive line is produced, followed by the deposition and planarization of a dielectric layer (such as an oxide layer), the formation of a trench in said dielectric layer, the filling of said trench with a conductive material and the planarization of said material, to obtain a second conductive line formed by the filled trench. The production technique allows to produce lines at a mutual distance of less than 500nm and having a width of less than 500nm, without losing the control over the width definition of the lines.

Abstract translation: 本发明涉及一种用于MEMS装置的表面上的生产传导平行线的方法。 在发明的方法中，第一导电线产生时，随之而来的是介电层的沉积和平坦化（颜色：诸如氧化层上），沟槽的所述介电层的形成，所述沟槽的填充有导电 材料和所述材料的平坦化，以获得由所述填充沟槽形成的第二导线。 生产技术允许在小于500nm的相互距离和具有小于500nm的宽度，以产生线条，而不会丢失在定义线的宽度的控制。

公开(公告)号：EP1916222A3

公开(公告)日：2013-02-27

申请号：EP07020581.0

申请日：2007-10-22

Applicant: Seiko Epson Corporation

Inventor： Watanabe, Toru ,  Sato, Akira ,  Inaba, Shogo ,  Mori, Takeshi

IPC: B81B3/00

CPC classification number: B81B3/0086 ,  B81B2201/0271

Abstract: A microelectromechanical system (MEMS) device includes a semiconductor substrate, a MEMS including a fixed electrode and a movable electrode formed on the semiconductor substrate through an insulating layer, and a well formed in the semiconductor substrate below the fixed electrode. The well is one of an n-type well and a p-type well. The p-type well applies a positive voltage to the fixed electrode while the n-type well applies a negative voltage to the fixed electrode.

公开(公告)号：EP2256084B1

公开(公告)日：2012-07-11

申请号：EP09161293.7

申请日：2009-05-27

Applicant: NXP B.V.

Inventor： Pohlmann, Hauke ,  Duemling, Martin ,  Dekker, Ronald ,  Mueller, Joerg

IPC: B81C1/00 ,  H03H3/007

CPC classification number: H03H3/0073 ,  B81B2201/0271 ,  B81C1/0019 ,  Y10T29/49005 ,  Y10T29/49128 ,  Y10T29/49156

公开(公告)号：EP2325135A1

公开(公告)日：2011-05-25

申请号：EP09176943.0

申请日：2009-11-24

Applicant: NXP B.V.

Inventor： Van Wingerden, Johannes ,  Van den Einden, Wim ,  Roosen, Harold H ,  Verheijden, Greja Johanna Adriana Maria ,  Koops, Gerhard ,  Ernur, Didem ,  Van Beek, Jozef Thomas Martinus

IPC: B81C1/00

CPC classification number: B81C1/00476 ,  B81B2201/0271 ,  B81C2203/0136 ,  B81C2203/0145 ,  H03H3/0072

Abstract: A method of packaging a micro electro-mechanical structure (122) comprises forming said structure (122) on a substrate (100); depositing a sacrificial layer (130) over said structure (122); patterning the sacrificial layer (130); depositing a SIPOS (semi-insulating polycrystalline silicon) layer (140) over the patterned sacrificial layer (130); treating the SIPOS layer (140) with an etchant to convert the SIPOS layer into a porous SIPOS layer, removing the patterned sacrificial layer (130) through the porous layer SIPOS (140) to form a cavity (150) including said structure (122); and sealing the porous SIPOS layer (140). A device including such a packaged micro electro-mechanical structure (122) is also disclosed.

Abstract translation: 一种封装微机电结构（122）的方法，包括：形成在基片，所述结构（122）（100）; 沉积在所述结构的牺牲层（130）（122）; 图案化所述牺牲层（130）; 沉积在所述图案化的牺牲层（130）中的SIPOS（半绝缘多晶硅）层（140）; 与蚀刻剂处理SIPOS层（140）到SIPOS层转换为多孔SIPOS层，通过多孔层SIPOS（140）去除所述图案化的牺牲层（130），以形成包括所述结构的腔体（150）（122） ; 并密封该多孔SIPOS层（140）。 包括寻求封装微机电结构的装置（122）IST游离缺失盘。

公开(公告)号：EP2138451B1

公开(公告)日：2011-05-25

申请号：EP09290471.3

申请日：2009-06-22

Applicant: Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Inventor： Perruchot, François ,  Diem, Bernard ,  Larrey, Vincent ,  Clavelier, Laurent ,  Defay, Emmanuel

IPC: B81C1/00 ,  H03H3/02

CPC classification number: B81C1/00507 ,  B81B2201/0271 ,  B81C2201/0115 ,  B81C2201/0136 ,  B81C2201/0177 ,  B81C2203/0136 ,  B81C2203/0145 ,  H03H3/0072 ,  H03H9/175 ,  H03H9/2436 ,  Y10S438/933

公开(公告)号：EP2235821A1

公开(公告)日：2010-10-06

申请号：EP08862478.8

申请日：2008-11-26

Applicant: Robert Bosch GmbH

Inventor： LUTZ, Markus ,  PAN, Zhiyu ,  PARTRIDGE, Aaron

IPC: H03H3/007 ,  H03H9/02 ,  B81B3/00

CPC classification number: H03H9/02244 ,  B81B3/007 ,  B81B3/0072 ,  B81B2201/0271 ,  B81B2203/0109 ,  B81B2203/0163 ,  H03H3/0076 ,  H03H9/02338 ,  H03H2009/0233 ,  H03H2009/02496 ,  H03H2009/02503

Abstract: A microelectromechanical resonator may include one or more resonator masses that oscillates in a bulk mode and that includes a first plurality of regions each having a density, and a second plurality of regions each having a density, the density of each of the second plurality of regions differing from the density of each of the first plurality of regions. The second plurality of regions may be disposed in a non-uniform arrangement. The oscillation may include a first state in which the resonator mass is contracted, at least in part, in a first and/or a second direction, and expanded, at least in part, in a third and/or a fourth direction, the second direction being opposite the first direction, the fourth direction being opposite the third direction.

公开(公告)号：EP2199252A1

公开(公告)日：2010-06-23

申请号：EP08022076.7

申请日：2008-12-18

Applicant: Epcos AG

Inventor： Zijlstra, Piebe Anne ,  Knotter, Dirk Marteen ,  van Weert, Jeroen ,  van Velzen, Bart

IPC: B81C1/00

CPC classification number: B81C1/00595 ,  B81B2201/0271 ,  B81C2201/0107 ,  B81C2201/0132 ,  B81C2203/0136

Abstract: A method of manufacturing a micro electro mechanical system (MEMS) device, comprising the steps of: providing a substrate, depositing an active layer, depositing a sacrificial layer, forming a MEMS structure in the active layer, wherein forming the MEMS structure comprises depositing a capping layer over the sacrificial layer, etching holes into the capping layer, removing the sacrificial layer with a dry etching process.

Abstract translation: 一种制造微机电系统（MEMS）器件的方法，包括以下步骤：提供衬底，沉积有源层，沉积牺牲层，在有源层中形成MEMS结构，其中形成MEMS结构包括： 覆盖在牺牲层上，将孔蚀刻到覆盖层中，用干蚀刻工艺去除牺牲层。

公开(公告)号：EP2138454A1

公开(公告)日：2009-12-30

申请号：EP09290474.7

申请日：2009-06-22

Applicant: Commissariat à l'Energie Atomique

Inventor： Perruchot, François ,  Diem, Bernard ,  Larrey, Vincent ,  Clavelier, Laurent ,  Defay, Emmanuel

IPC: B81C1/00 ,  H03H3/007

CPC classification number: B81C1/00595 ,  B81B2201/0271 ,  B81C2201/0109 ,  B81C2201/014

Abstract: L'Invention se rapporte à un procédé de réalisation d'un composant à partir d'un substrat hétérogène comportant une première et une deuxième parties en au moins un matériau monocristallin, et une couche sacrificielle constituée par au moins un empilement d'au moins une couche de Si monocristallin située entre deux couches de SiGe monocristallin, cet empilement étant disposé entre lesdites première et deuxième partie en matériau monocristallin, caractérisé en ce qu'il consiste à graver ledit empilement en réalisant :
e) au moins une ouverture (20) dans la première et/ou la deuxième parties et la première et/ou la deuxième couche de SiGe de façon à déboucher sur la couche de Si,
f) une élimination de toute ou partie de la couche de Si.

Abstract translation: 基板具有由位于单晶硅 - 锗层之间的单晶硅层（3）的叠层构成的牺牲层。 堆栈是位于两个单晶部分之间。 一个单晶的部分之一是含有一个硅 - 锗材料的外延相容。 另一单晶硅部分是硅，钛酸锶/锆钛酸铅，或锶/钌酸锶/锆钛酸铅中选择。 因此独立权利要求中包括了以下内容：为了实现异质衬底（2）的方法，用于从异质衬底实现一个部件（1）的方法。