公开(公告)号：US10276366B2

公开(公告)日：2019-04-30

申请号：US14821203

申请日：2015-08-07

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Xinyu Liu ,  Sen Huang ,  Xinhua Wang ,  Ke Wei ,  Wenwu Wang ,  Junfeng Li ,  Chao Zhao

IPC: H01L21/02 ,  C23C16/02 ,  C23C16/30

Abstract: A method for manufacturing a low interface state device includes performing a remote plasma surface process on a III-Nitride layer on a substrate; transferring the processed substrate to a deposition cavity via an oxygen-free transferring system; and depositing on the processed substrate in the deposition cavity. The deposition may be low pressure chemical vapor deposition (LPCVD). The interface state between a surface dielectric and III-Nitride material may be significantly decreased by integrating a low impairment remote plasma surface process and LPCVD.

公开(公告)号：US20190067466A1

公开(公告)日：2019-02-28

申请号：US15781988

申请日：2016-06-27

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong ZHU

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02 ,  H01L21/762 ,  H01L21/308

Abstract: A semiconductor device having a high-quality epitaxial layer and a method of manufacturing the same are provided. According to an embodiment, the semiconductor device may include: a substrate; a first fin-shaped semiconductor layer spaced apart from the substrate, wherein the first semiconductor layer extends along a curved longitudinal extending direction; and a second semiconductor layer at least partially surrounding a periphery of the first semiconductor layer.

公开(公告)号：US20190013383A1

公开(公告)日：2019-01-10

申请号：US15759102

申请日：2015-09-10

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES ,  ZHUZHOU CRRC TIMES ELECTRIC CO., LTD.

Inventor： Yidan TANG ,  Huajun SHEN ,  Yun BAI ,  Jingtao ZHOU ,  Chengyue YANG ,  Xinyu LIU ,  Chengzhan LI ,  Guoyou LIU

IPC: H01L29/16 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/04 ,  H01L21/324 ,  H01L27/092

Abstract: The present disclosure discloses a self-aligned silicon carbide MOSFET device with an optimized P+ region and a manufacturing method thereof. The self-aligned silicon carbide MOSFET device is formed by a plurality of silicon carbide MOSFET device cells connected in parallel, and these silicon carbide MOSFET device cells are arranged evenly. The silicon carbide MOSFET device cell comprises two source electrodes, one gate electrode, one gate oxide layer, two N+ source regions, two P+ contact regions, two P wells, one N- drift layer, one buffer layer, one N+ substrate, one drain electrode and one isolation dielectric layer. By optimizing the P+ region, the present disclosure forms a good source ohmic contact, reduces the on-resistance, and also shorts the source electrode and the P well to prevent the parasitic transistor effect of the parasitic NPN and PiN, which may take both conduction characteristics and the breakdown characteristics of the device into consideration, and may be applied to a high voltage, high frequency silicon carbide MOSFET device. The self-aligned manufacturing method used in the present disclosure simplifies the process, controls a size of a channel accurately, and may produce a lateral and vertical power MOSFET.

公开(公告)号：US20190006584A1

公开(公告)日：2019-01-03

申请号：US16064120

申请日：2016-08-12

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Nianduan LU ,  Pengxiao SUN ,  Ling LI ,  Ming IIU ,  Qi LIU ,  Hangbing LV ,  Shibing LONG

IPC: H01L45/00

Abstract: A method for improving endurance of 3D integrated resistive switching memory, comprising: Step 1: Calculating the temperature distribution in the integrated array by the 3D Fourier heat conduction equation; Step 2, selecting heat transfer mode; Step 3: selecting an appropriate array structure; Step 4: analyzing the influence of integration degree on temperature in the array; Step 5: evaluating the endurance performance in the array; and Step 6: changing the array parameters according to the evaluation result to improve the endurance performance. According to the method of the present invention, based on the thermal transmission mode in the 3D integrated resistive switching device, a suitable 3D integrated array is selected to analyze the influence of the integration degree on the device temperature so as to evaluate and improve the endurance of the 3D integrated resistive switching device.

公开(公告)号：US20180366643A1

公开(公告)日：2018-12-20

申请号：US16064116

申请日：2016-08-12

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Nianduan Lu ,  Pengxiao Sun ,  Ling Li ,  Ming Iiu ,  Qi Liu ,  Hangbing Lv ,  Shibing Long

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00 ,  G01N25/20

CPC classification number: H01L45/128 ,  G01N25/20 ,  G11C7/04 ,  G11C13/0002 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/00 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1293

Abstract: A method for evaluating the thermal effects of 3D RRAM arrays and reducing thermal crosstalk, including the following steps: Step 1: calculating the temperature distribution in the array through 3D Fourier heat conduction equation; Step 2, selecting a heat transfer mode; Step 3, selecting an appropriate array structure; Step 4, analyzing the effect of position of programming device in the array on the temperature; Step 5, analyzing the thermal crosstalk effect in the array; Step 6, evaluating thermal effects and thermal crosstalk; Step 7, changing the array structure or modify operating parameters based on the evaluation results to reduce the thermal crosstalk. According to the method of the present invention, the influence of the position of the device on the temperature is analyzed according to the heat transfer mode of the 3D RRAM array, the thermal effect and the thermal crosstalk are evaluated, and the appropriate array structure and operating parameters are selected according to the evaluation result, which effectively improves the thermal stability of the device.

公开(公告)号：US10128351B2

公开(公告)日：2018-11-13

申请号：US14389095

申请日：2012-10-08

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu ,  Qingqing Liang ,  Huicai Zhong

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/49 ,  H01L21/28 ,  H01L27/11568 ,  H01L21/8238 ,  H01L29/423

Abstract: Semiconductor devices and methods of manufacturing the same are provided. In one embodiment, the method may include: forming a first shielding layer on a substrate; forming one of source and drain regions with the first shielding layer as a mask; forming a second shielding layer on the substrate, and removing the first shielding layer; forming a shielding spacer on a sidewall of the second shielding layer; forming the other of the source and drain regions with the second shielding layer and the shielding spacer as a mask; removing at least a portion of the shielding spacer; and forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of the second shielding layer or a possible remaining portion of the shielding spacer.

公开(公告)号：US20180315769A1

公开(公告)日：2018-11-01

申请号：US15770020

申请日：2015-11-23

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Zongliang Huo ,  Tianchun Ye

IPC: H01L27/11582 ,  H01L29/10

CPC classification number: H01L21/8239 ,  H01L27/105 ,  H01L27/115 ,  H01L29/10

Abstract: A three-dimensional semiconductor device includes: A peripheral circuit, distributed on a substrate; a plurality of memory cells above the peripheral circuit, each of which includes: a common source region, between the memory cell and the peripheral circuit; a channel layer, distributed in a direction perpendicular to the surface of the substrate; at least one substrate contact layer, extending horizontally from the central portion of the channel layer parallel to the surface of the substrate, each comprising at least one substrate contact region; a plurality of insulating layers, located on sidewalls of the channel layer; a plurality of control gates, sandwiched between adjacent insulating layers; a gate dielectric layer, located between the channel layer and the control gates; a drain region, located at top of the channel layer; a substrate contact lead-out line, electrically connected to the substrate contact regions; and a bit line wiring, electrically connected to the drain region of each memory cell and the peripheral circuit. The substrate contact regions are formed in the middle of the memory strings, improving the erase/write performance and reliability of the memory, increasing the density of the storage array, reducing the entire memory chip area and saving the costs.

公开(公告)号：US10115641B2

公开(公告)日：2018-10-30

申请号：US15718610

申请日：2017-09-28

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/225 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/04 ,  H01L29/78

Abstract: There are provided a semiconductor arrangement, a method of manufacturing the same, and an electronic device including the semiconductor arrangement. According to an embodiment, the semiconductor arrangement may include a first semiconductor device and a second semiconductor device stacked in sequence on a substrate. Each of the first semiconductor device and the second semiconductor device may include a first source/drain layer, a channel layer and a second source/drain layer stacked in sequence, and a gate stack surrounding a periphery of the channel layer. The channel layer may comprise a semiconductor material different from that of the first source/drain layer and from that of the second source/drain layer.

公开(公告)号：US20180294342A1

公开(公告)日：2018-10-11

申请号：US15871690

申请日：2018-01-15

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Jinjuan XIANG ,  Xiaolei WANG ,  Hong YANG ,  Shi LIU ,  Junfeng LI ,  Wenwu WANG ,  Chao ZHAO

IPC: H01L29/66 ,  H01L29/49 ,  H01L21/265

CPC classification number: H01L29/66545 ,  H01L21/265 ,  H01L29/4966

Abstract: The present disclosure provides a method for manufacturing a transistor having a gate with a variable work function, comprising: providing a semiconductor substrate; forming a dummy gate stack on the semiconductor substrate and performing ion implantation on an exposed area of the semiconductor substrate at both sides of the dummy gate stack to form source/drain regions; removing the dummy gate and annealing the source/drain regions; providing an atomic layer deposition reaction device; introducing a precursor source reactant into the atomic layer deposition reaction device; and controlling an environmental factor for the atomic layer deposition device to grow a work function metal layer. The present disclosure also provides a transistor having a gate with a variable work function. The present disclosure may adjust a variable work function, and may use the same material system to obtain an adjustable threshold voltage within an adjustable range.

公开(公告)号：US10056261B2

公开(公告)日：2018-08-21

申请号：US14385101

申请日：2012-12-07

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu ,  Qiuxia Xu ,  Yanbo Zhang ,  Hong Yang

IPC: H01L21/28 ,  H01L21/266 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/265 ,  H01L21/268

CPC classification number: H01L21/28008 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/268 ,  H01L21/28088 ,  H01L21/28167 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7833

Abstract: Provided are P type MOSFETs and methods for manufacturing the same. The method may include forming source/drain regions in a semiconductor substrate; forming an interfacial oxide layer on the semiconductor substrate; forming a high K gate dielectric layer on the interfacial oxide layer; forming a first metal gate layer on the high K gate dielectric layer; implanting dopants into the first metal gate layer through conformal doping; and performing annealing to change an effective work function of a gate stack including the first metal gate layer, the high K gate dielectric, and the interfacial oxide layer.