公开(公告)号：US20060049519A1

公开(公告)日：2006-03-09

申请号：US11211764

申请日：2005-08-26

Applicant: Tetsuya Otsuki

Inventor： Tetsuya Otsuki

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L24/32 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/04042 ,  H01L2224/16 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L2224/92247 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/181 ,  H05K1/111 ,  H05K3/243 ,  H05K3/3457 ,  H05K2201/0373 ,  H05K2201/09663 ,  H05K2201/09745 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01083 ,  H01L2924/00012 ,  H01L2924/3512

Abstract: A semiconductor device, comprises: a carrier substrate in which a semiconductor chip is mounted; and a land formed in the carrier substrate and arranged in a region different from the mounting face of the semiconductor chip, wherein a coarse face, the surface roughness of which is 20 through 100 μm, is formed in a bonding face of the land.

Abstract translation: 一种半导体器件，包括：其中安装有半导体芯片的载体基板; 以及形成在所述载体基板中并且布置在与所述半导体芯片的安装面不同的区域中的区域，其中在所述焊盘的接合面中形成表面粗糙度为20-100μm的粗糙面。

公开(公告)号：US06980017B1

公开(公告)日：2005-12-27

申请号：US09266237

申请日：1999-03-10

Applicant: Warren M. Farnworth ,  Salman Akram

Inventor： Warren M. Farnworth ,  Salman Akram

IPC: G01R1/04 ,  H05K1/11 ,  H05K3/32 ,  H05K3/40 ,  G01R31/02 ,  G01R31/26

CPC classification number: H05K3/326 ,  G01R1/0466 ,  G01R31/2853 ,  H05K1/118 ,  H05K3/4092 ,  H05K2201/0373 ,  H05K2201/0397 ,  H05K2201/09036 ,  H05K2201/09081 ,  H05K2201/10734 ,  Y10T29/49117 ,  Y10T29/49121 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/4914 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: An interconnect for testing semiconductor components includes a substrate, and contacts on the substrate for making temporary electrical connections with bumped contacts on the components. Each contact includes a recess and a pattern of leads cantilevered over the recess configured to electrically engage a bumped contact. The leads are adapted to move in a z-direction within the recess to accommodate variations in the height and planarity of the bumped contacts. In addition, the leads can include projections for penetrating the bumped contacts, a non-bonding outer layer for preventing bonding to the bumped contacts, and a curved shape which matches a topography of the bumped contacts. The leads can be formed by forming a patterned metal layer on the substrate, by attaching a polymer substrate with the leads thereon to the substrate, or be etching the substrate to form conductive beams.

Abstract translation: 用于测试半导体部件的互连件包括基板和基板上的触点，用于与部件上的凸起触点进行临时电连接。 每个接触件包括一个凹部和悬在该凹部上的引线图案，其构造成电接合凸起的触点。 引线适于在凹部内在z方向上移动以适应凸起接触件的高度和平面度的变化。 此外，引线可以包括用于穿透凸起的触点的突起，用于防止与凸起的触点接合的非结合外层以及与凸起的触点的形状相匹配的弯曲形状。 可以通过在基板上形成图案化的金属层，通过将聚合物基板与其上的引线附接到基板上，或者蚀刻基板以形成导电梁来形成引线。

公开(公告)号：US20040257193A1

公开(公告)日：2004-12-23

申请号：US10688458

申请日：2003-10-17

Applicant: Shipley Company, L.L.C.

Inventor： Craig S. Allen ,  Andrew T. Hunt ,  Wen-Yi Lin ,  David D. Senk ,  John Schemenaur

IPC: H01C001/012

CPC classification number: H01C17/065 ,  H05K1/167 ,  H05K3/025 ,  H05K2201/0355 ,  H05K2201/0373 ,  H05K2203/0361

Abstract: Resistive materials have resistivities that are axis dependent are provided. Such resistive materials having a resistivity in a first direction and a very different resistivity in an orthogonal direction. These resistive materials are particularly suitable for use as resistors embedded in printed wiring boards.

Abstract translation: 电阻材料具有轴向依赖性的电阻率。 这种电阻材料在正交方向具有第一方向的电阻率和非常不同的电阻率。 这些电阻材料特别适用于嵌入印刷电路板的电阻器。

公开(公告)号：US06815613B2

公开(公告)日：2004-11-09

申请号：US09951823

申请日：2001-09-13

Applicant: Uta Gebauer ,  Volker Strutz

Inventor： Uta Gebauer ,  Volker Strutz

IPC: H02G308

CPC classification number: H01L24/16 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05568 ,  H01L2224/13099 ,  H01L2224/16105 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81801 ,  H01L2224/81898 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19043 ,  H05K3/3436 ,  H05K3/4015 ,  H05K2201/0373 ,  H05K2201/09427 ,  H05K2201/10242 ,  Y02P70/613 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: The invention relates to an electronic component with external connection elements and to a method of electrically connecting and/or fixing an electronic component to a printed-circuit board. For this purpose, the electronic component has capillary elements as external connection elements, which are connected to contact connection areas of a leadframe or to contact areas of a chip. The capillary element protrudes out of the electronic component and has, on its protruding end, a suction opening with capillary action.

Abstract translation: 本发明涉及一种具有外部连接元件的电子元件以及将电子元件电连接和/或固定到印刷电路板的方法。 为此，电子部件具有作为外部连接元件的毛细管元件，其连接到引线框架的接触连接区域或接触芯片的区域。 毛细管元件从电子部件突出，并且在其突出端具有毛细管作用的抽吸开口。

公开(公告)号：US20040174178A1

公开(公告)日：2004-09-09

申请号：US10803294

申请日：2004-03-17

Inventor： Warren M. Farnworth ,  Malcolm Grief ,  Gurtej S. Sandhu

IPC: G01R031/02

CPC classification number: G01R1/07314 ,  H01L2924/00013 ,  H05K1/0306 ,  H05K3/325 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/09045 ,  Y10S438/978 ,  Y10T29/49117 ,  Y10T29/49204 ,  H01L2224/29099

Abstract: A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a) providing an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate; b) engaging the grouping of apexes with the single test pad on the semiconductor substrate; and c) sending an electric signal between the grouping of apexes and test pad to evaluate operability of integrated circuitry on the semiconductor substrate. Constructions and methods are disclosed for forming testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.

公开(公告)号：US20040095158A1

公开(公告)日：2004-05-20

申请号：US10703763

申请日：2003-11-07

Inventor： Warren M. Farnworth ,  Malcolm Grief ,  Gurtej S. Sandhu

IPC: G01R031/26

CPC classification number: G01R1/07314 ,  H01L2924/00013 ,  H05K1/0306 ,  H05K3/325 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/09045 ,  Y10S438/978 ,  Y10T29/49117 ,  Y10T29/49204 ,  H01L2224/29099

Abstract: A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a) providing an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate; b) engaging the grouping of apexes with the single test pad on the semiconductor substrate; and c) sending an electric signal between the grouping of apexes and test pad to evaluate operability of integrated circuitry on the semiconductor substrate. Constructions and methods are disclosed for forming testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.

Abstract translation: 一种在具有用于其可操作性测试的集成电路的半导体衬底上接合导电测试焊盘的方法包括：a）提供具有外表面的接合探针，该外表面包括彼此靠近定位的多个导电突出顶点的组， 半导体衬底上的单个测试焊盘; b）使顶点的分组与半导体衬底上的单个测试焊盘接合; 以及c）在顶点组和测试垫之间发送电信号，以评估半导体衬底上的集成电路的可操作性。 公开了用于形成测试装置的结构和方法，所述测试装置包括具有外表面的接合探针，所述外表面包括彼此靠近地定位的多个导电突出顶点的组，以接合半导体衬底上的单个测试焊盘。

公开(公告)号：US06670819B2

公开(公告)日：2003-12-30

申请号：US10057711

申请日：2002-01-24

Applicant: Warren M. Farnworth ,  Malcolm Grief ,  Gurtej S. Sandhu

Inventor： Warren M. Farnworth ,  Malcolm Grief ,  Gurtej S. Sandhu

IPC: G01R3102

CPC classification number: G01R1/07314 ,  H01L2924/00013 ,  H05K1/0306 ,  H05K3/325 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/09045 ,  Y10S438/978 ,  Y10T29/49117 ,  Y10T29/49204 ,  H01L2224/29099

Abstract: A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a) providing an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate; b) engaging the grouping of apexes with the single test pad on the semiconductor substrate; and c) sending an electric signal between the grouping of apexes and test pad to evaluate operability of integrated circuitry on the semiconductor substrate. Constructions and methods are disclosed for forming testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.

公开(公告)号：US20030234277A1

公开(公告)日：2003-12-25

申请号：US10183874

申请日：2002-06-25

Inventor： Rajen Dias ,  Biju Chandran

IPC: B23K031/00

CPC classification number: H05K3/3436 ,  H01L21/563 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11 ,  H01L2224/1147 ,  H01L2224/13 ,  H01L2224/13011 ,  H01L2224/13015 ,  H01L2224/13099 ,  H01L2224/73203 ,  H01L2224/81193 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H05K3/321 ,  H05K2201/0367 ,  H05K2201/0373 ,  Y02P70/613 ,  Y10T428/24917 ,  Y10T428/31681 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A microelectronic assembly including a plurality of conductive columns extending from a bond pad of a microelectronic device and a conductive adhesive on a land pad of a carrier substrate electrically attached to the conductive columns.

Abstract translation: 一种微电子组件，包括从微电子器件的接合焊盘延伸的多个导电柱和电连接到导电柱的载体衬底的焊盘上的导电粘合剂。

公开(公告)号：US06651323B2

公开(公告)日：2003-11-25

申请号：US09851064

申请日：2001-05-07

Applicant: Ted B Ziemkowski

Inventor： Ted B Ziemkowski

IPC: H01R900

CPC classification number: H05K1/0209 ,  H05K1/111 ,  H05K2201/0373 ,  H05K2201/09781 ,  H05K2201/10166 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A method for manufacturing a surface mount solder pad that is adapted to function as a heat sink for an electronic component soldered to the pad. The method comprises a step of providing a printed wiring board having a conductive layer disposed thereon. The method further comprises a step of selecting a size and arrangement of regions of a solder pad so as to sink sufficient heat. The method also comprises removing non-selected regions of the conductive layer to produce solder pads on the surface of the printed wiring board enhanced with features that promote heat transfer to sink enough heat generated by one of the surface mount components to provide for its proper operation.

Abstract translation: 一种用于制造表面贴装焊盘的方法，其适于用作焊接到焊盘的电子部件的散热器。 该方法包括提供其上布置有导电层的印刷线路板的步骤。 该方法还包括选择焊盘的区域的尺寸和布置以便吸收足够的热量的步骤。 该方法还包括去除导电层的未选择的区域，以在印刷线路板的表面上产生焊盘，其特征在于促进热传递以吸收由一个表面安装部件产生的足够的热量以提供其适当的操作 。

公开(公告)号：US20030180011A1

公开(公告)日：2003-09-25

申请号：US10285772

申请日：2002-11-01

Inventor： Lewis B. Aronson

IPC: G02B006/42

CPC classification number: H05K1/117 ,  G02B6/43 ,  H01R12/721 ,  H01R13/6585 ,  H05K1/0216 ,  H05K2201/0373 ,  H05K2201/093 ,  H05K2201/094 ,  H05K2201/09681 ,  H05K2201/09727

Abstract: An impedance-matching electrical connection system, for use with high-frequency communication signals, includes a circuit board and a plurality of contact pads mounted on the circuit board. The contact pads are for coupling with a plurality of complementary connectors of an external electrical device. Each coupling is associated with an excess shunt capacitance. The electrical connection system further includes a plurality of inductive traces mounted on the circuit board, each of which is connected to a respective contact pad, and is associated with a compensating series inductance. Additionally, the electrical connection system includes a plurality of signal lines mounted on the circuit board, each of which is connected to a respective inductive trace. Each inductive trace is configured so that its associated compensating series inductance substantially offsets the excess shunt capacitance associated with the coupling between the contact pad connected to the inductive trace and a complementary connector.

Abstract translation: 用于高频通信信号的阻抗匹配电连接系统包括电路板和安装在电路板上的多个接触焊盘。 接触垫用于与外部电气设备的多个互补连接器耦合。 每个耦合与多余的并联电容相关联。 电连接系统还包括安装在电路板上的多个感应迹线，每个感应迹线连接到相应的接触焊盘，并与补偿串联电感相关联。 此外，电连接系统包括安装在电路板上的多条信号线，每条信号线连接到相应的电感迹线上。 每个电感迹线配置成使得其相关联的补偿串联电感基本上抵消与连接到电感迹线的接触焊盘和互补连接器之间的耦合相关联的过量分流电容。