公开(公告)号：US08110929B2

公开(公告)日：2012-02-07

申请号：US12602462

申请日：2008-05-27

Applicant: Toshikazu Imaoka ,  Tetsuro Sawai ,  Kenichi Kobayashi ,  Atsushi Nakano

Inventor： Toshikazu Imaoka ,  Tetsuro Sawai ,  Kenichi Kobayashi ,  Atsushi Nakano

IPC: H01L23/48

CPC classification number: H05K1/141 ,  H01L24/73 ,  H01L25/0657 ,  H01L2223/6638 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15174 ,  H01L2924/15182 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/181 ,  H05K1/182 ,  H05K3/3436 ,  H05K2201/09136 ,  H05K2201/09418 ,  H05K2201/10545 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A semiconductor module includes: a substrate having a wiring layer; a first rectangular-shaped semiconductor device mounted on one surface of the substrate; a second rectangular-shaped semiconductor device mounted on the other surface of the substrate. The first semiconductor device is arranged such that each side thereof is not parallel to that of the second semiconductor device, and that the first semiconductor device is superimposed on the second semiconductor device, when seen from the direction perpendicular to the surface of the substrate.

Abstract translation: 半导体模块包括：具有布线层的基板; 安装在所述基板的一个表面上的第一矩形半导体器件; 安装在所述基板的另一表面上的第二矩形半导体器件。 第一半导体器件布置成使得其每侧不与第二半导体器件的平行平行，并且当从垂直于衬底的表面的方向看时，第一半导体器件重叠在第二半导体器件上。

公开(公告)号：US08016967B2

公开(公告)日：2011-09-13

申请号：US12605442

申请日：2009-10-26

Applicant: Yoshifumi Saito

Inventor： Yoshifumi Saito

IPC: C03B29/00 ,  B32B7/02 ,  B32B19/00

CPC classification number: H05K3/4611 ,  B32B18/00 ,  C04B2235/6025 ,  C04B2235/6567 ,  C04B2237/341 ,  C04B2237/343 ,  C04B2237/562 ,  C04B2237/62 ,  C04B2237/66 ,  C04B2237/68 ,  C04B2237/702 ,  C04B2237/704 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/19105 ,  H05K1/0306 ,  H05K3/4629 ,  H05K2201/09136 ,  H05K2203/308 ,  Y10T428/2495 ,  H01L2224/0401

Abstract: In the manufacture of a multilayer ceramic substrate including a ceramic laminate by a so-called non-shrink process in which the ceramic laminate disposed between shrinkage control layers is fired, first and second surface conductive films formed on first and second main surfaces of the ceramic laminate may cause warping of the multilayer ceramic substrate after the shrinkage control layers are removed. After the firing step, in removing the shrinkage control layers from a composite laminate, the thickness of at least one of first and second reaction layers formed at interfaces between ceramic green layers and the shrinkage control layers in the firing step is reduced such that the thickness of the first reaction layer is different from the thickness of the second reaction layer, thereby controlling the compressive stress generated by the reaction layers to reduce the warping of the multilayer ceramic substrate.

Abstract translation: 在通过所谓的非收缩工艺制造包括陶瓷层压体的多层陶瓷基板中，其中烧结收缩控制层之间的陶瓷层压体被烧制，形成在陶瓷的第一和第二主表面上的第一和第二表面导电膜 在除去收缩控制层之后，层压体可能导致多层陶瓷基板的翘曲。 在烧成工序之后，从复合层叠体除去收缩控制层时，在烧成工序中，陶瓷生坯层与收缩控制层的界面处形成的第一反应层和第二反应层中的至少一个的厚度减小， 的第一反应层的厚度与第二反应层的厚度不同，从而控制由反应层产生的压缩应力，以减少多层陶瓷基板的翘曲。

公开(公告)号：US20110108982A1

公开(公告)日：2011-05-12

申请号：US12835043

申请日：2010-07-13

Applicant: Seong Cheol Kim ,  Chang Jun Park

Inventor： Seong Cheol Kim ,  Chang Jun Park

IPC: H01L23/488 ,  H05K1/11 ,  H05K1/09

CPC classification number: H01L23/488 ,  H01L24/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/3511 ,  H05K1/111 ,  H05K1/112 ,  H05K3/3436 ,  H05K2201/0191 ,  H05K2201/09136 ,  H05K2201/094 ,  H05K2201/09436 ,  H05K2201/09736 ,  Y02P70/613

Abstract: A printed circuit board includes a body part formed with connection pads on a first surface thereof; and a warpage compensating part formed over the first surface of the body part and having a height that increases from edges toward a center of the warpage compensating part so that an upper surface of the warpage compensating part facing away from the first surface of the body part is convex upward. The warpage compensating part comprises conductive layer patterns formed over the first surface of the body part to be electrically connected to the connection pads; and a solder resist formed over the first surface of the body part so as to expose the conductive layer patterns. The height of the solder resist gradually increases from both edges toward a center of the solder resist.

Abstract translation: 印刷电路板包括在其第一表面上形成有连接焊盘的主体部分; 以及翘曲补偿部，其形成在主体部的第一表面上，并且具有从边缘朝向翘曲补偿部的中心增大的高度，使得翘曲补偿部的上表面背离主体部的第一表面 向上凸起 翘曲补偿部分包括形成在主体部分的第一表面上以电连接到连接焊盘的导电层图案; 以及形成在主体部分的第一表面上的阻焊剂，以暴露导电层图案。 阻焊剂的高度从阻焊层的两个边缘向中心逐渐增加。

公开(公告)号：US20110075386A1

公开(公告)日：2011-03-31

申请号：US12873702

申请日：2010-09-01

Applicant: Hiroaki Tamura ,  Fumihiko Tokura ,  Michinao Nomura ,  Toshihiro Kusagaya ,  Kazuhiro Mizukami

Inventor： Hiroaki Tamura ,  Fumihiko Tokura ,  Michinao Nomura ,  Toshihiro Kusagaya ,  Kazuhiro Mizukami

IPC: H05K7/14 ,  H01R4/02 ,  H05K1/18

CPC classification number: H05K3/3426 ,  H01L23/495 ,  H01L23/49548 ,  H01L23/49555 ,  H01L23/49582 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/181 ,  H05K2201/09136 ,  H05K2201/10189 ,  H05K2201/10689 ,  H05K2201/10787 ,  H05K2201/10909 ,  H05K2201/10946 ,  H05K2201/10984 ,  Y02P70/613 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: An electronic component includes: an electronic component body; and a lead secured to the electric component and including a projection portion defined by first and second inclined portions facing each other. The solder wettability of the first inclined portion is smaller than the solder wettability of the second inclined portion.

Abstract translation: 电子部件包括：电子部件主体; 以及固定到电气部件的引线，并且包括由彼此面对的第一和第二倾斜部限定的突出部。 第一倾斜部分的焊料润湿性小于第二倾斜部分的焊料润湿性。

公开(公告)号：US20100238634A1

公开(公告)日：2010-09-23

申请号：US12443723

申请日：2007-09-28

Applicant: Tadashi Matsuzawa

Inventor： Tadashi Matsuzawa

IPC: H05K7/14

CPC classification number: H05K7/1461 ,  H05K1/0271 ,  H05K2201/09136 ,  H05K2201/10393

Abstract: A correcting fitting clamped by elasticity at least on one part of an edge portion of a printed circuit board for correcting warpage or flexure of the printed circuit board. The correcting fitting has a clamping portion for coming into band-shaped abutting contact with both faces of the printed circuit board along the edge portion of the printed circuit board. The clamping portion is bent in such a manner that at least a portion thereof is directed toward the edge portion of the printed circuit board. The bending strength of the correcting fitting against warpage and flexure of the printed circuit board can be enhanced by the clamping portion. Further, since fixing elements such as screws are not used to mount the correcting fitting, the number of parts of the printed circuit board and the number of steps for assembling the same can be reduced to thereby lower cost and achieve high-density packaging.

Abstract translation: 用于校正印刷电路板的翘曲或弯曲的至少在印刷电路板的边缘部分的一部分上由弹性夹紧的校正配件。 校正配件具有夹持部分，用于沿着印刷电路板的边缘部分与印刷电路板的两个表面形成邻接接触。 夹持部弯曲成使得其至少一部分朝向印刷电路板的边缘部分。 可以通过夹紧部分来增强校正配件抵抗印刷电路板翘曲和挠曲的弯曲强度。 此外，由于不使用诸如螺钉的固定元件来安装校正配件，所以可以减少印刷电路板的部件数量和组装步骤的数量，从而降低成本并实现高密度封装。

公开(公告)号：US07799603B2

公开(公告)日：2010-09-21

申请号：US12466361

申请日：2009-05-14

Applicant: Chung-Jen Tsai ,  Chia-Cheng Chen ,  Hung-Yi Chang ,  Tung-Yao Kuo ,  Cheng-Hsien Lin

Inventor： Chung-Jen Tsai ,  Chia-Cheng Chen ,  Hung-Yi Chang ,  Tung-Yao Kuo ,  Cheng-Hsien Lin

IPC: H01L21/52

CPC classification number: H05K1/0271 ,  H05K3/0052 ,  H05K3/303 ,  H05K3/341 ,  H05K2201/09127 ,  H05K2201/09136 ,  H05K2201/09681 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2201/2009

Abstract: A method for assembling an electronic component on a printed circuit board includes following steps. Firstly, a printed circuit board substrate including a central main portion and a peripheral unwanted portion is provided. Secondly, electrically conductive patterns and reinforcing patterns are formed on the main portion and the unwanted portion respectively. Thirdly, an electronic component is mounted on the main portion and electrically connected with the electrically conductive patterns. Fifthly, the unwanted portion is removed.

Abstract translation: 一种用于在印刷电路板上组装电子部件的方法包括以下步骤。 首先，提供包括中央主要部分和外围不想要的部分的印刷电路板基板。 其次，分别在主要部分和不想要的部分上形成导电图案和加强图案。 第三，电子部件安装在主体部分上并与导电图形电连接。 第五，去除不想要的部分。

公开(公告)号：US20100139962A1

公开(公告)日：2010-06-10

申请号：US12628284

申请日：2009-12-01

Applicant: Kentaro KANEKO

Inventor： Kentaro KANEKO

IPC: H05K1/16 ,  H05K3/00

CPC classification number: H05K3/0014 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/32 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83051 ,  H01L2224/83385 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/112 ,  H05K3/305 ,  H05K3/4682 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09136 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/0401

Abstract: A wiring board includes a structure in which a plurality of wiring layers are stacked one on top of another with an insulating layer (resin layer) interposed therebetween, and the wiring layers are connected to each other through a via formed in each of the resin layers. A recessed portion is formed in an annular shape surrounding a chip mounting area on the outermost resin layer on a chip mounting surface side of the wiring board. Alternatively, a projected portion is formed instead of the recessed portion.

Abstract translation: 布线基板包括其中多个布线层一层叠置在其上的绝缘层（树脂层）之间的结构，并且布线层通过形成在每个树脂层中的通孔相互连接 。 凹陷部形成为围绕布线基板的芯片安装面侧的最外层树脂层上的芯片安装区域的环状。 或者，形成突出部分而不是凹部。

公开(公告)号：US20090276164A1

公开(公告)日：2009-11-05

申请号：US12306491

申请日：2008-06-25

Applicant: Ichiro Hirata

Inventor： Ichiro Hirata

IPC: G06F19/00 ,  G06F15/00

CPC classification number: G06F17/5009 ,  G06F17/5068 ,  G06F2217/40 ,  G06F2217/80 ,  H05K3/00 ,  H05K3/0005 ,  H05K2201/09136

Abstract: The board warp analysis method includes, in board warp calculation based on model data including at least a configuration and an elastic constant of a board and an electronic component including various kinds of parts which is mounted on the board, the processing of dividing a temperature profile indicative of a relationship between a temperature and a time with respect to the electronic component by a predetermined time, obtaining a relaxation elastic modulus of the electronic component corresponding to the divisional time by shifting on a time base of a master curve related to the electronic component which is composed with respect to a reference temperature based on a temperature-time conversion rule, calculating a curing degree of the electronic component based on a relationship between a time after shift and an actually applied temperature, and analyzing a warp of the electronic component based on a relaxation elastic modulus on the master curve corresponding to the curing degree or a relaxation elastic modulus calculated based on a relationship between the curing degree and the elastic constant according to a value of the curing degree calculated.

Abstract translation: 板翘曲分析方法包括：基于包括板的构造和弹性常数的模型数据的板翘曲计算和包括安装在板上的各种部件的电子部件，分割温度分布的处理 指示相对于电子部件的温度和时间之间的关系预定时间，通过基于与电子部件相关的主曲线的时基移位来获得与分时间相对应的电子部件的松弛弹性模量 其基于温度 - 时间转换规则相对于参考温度而组合，基于移位后的时间与实际施加的温度之间的关系计算电子部件的固化度，并且基于电子部件的翘曲来分析 对应于固化度的主曲线上的松弛弹性模量 或者根据所计算的固化度的值，根据固化度与弹性常数的关系计算松弛弹性模量。

公开(公告)号：US20090250802A1

公开(公告)日：2009-10-08

申请号：US12382546

申请日：2009-03-18

Applicant: Yuichi Miyagawa

Inventor： Yuichi Miyagawa

IPC: H01L23/02 ,  H05K1/02 ,  H01L21/50 ,  H01L23/48

CPC classification number: H01L23/49822 ,  H01L23/49894 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/068 ,  H05K2201/09136 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A multilayer wiring substrate included in the semiconductor package includes: a first insulating layer and a second insulating layer, in which wiring layers are respectively provided on the upper and the lower surfaces; and; a core layer provided between the first insulating layer and the second insulating layer. The first insulating layer and the second insulating layer are constituted by different materials from each other.

Abstract translation: 包括在半导体封装中的多层布线基板包括：第一绝缘层和第二绝缘层，其中布线层分别设置在上表面和下表面上; 和; 芯层，设置在第一绝缘层和第二绝缘层之间。 第一绝缘层和第二绝缘层由彼此不同的材料构成。

公开(公告)号：US20090133915A1

公开(公告)日：2009-05-28

申请号：US11719313

申请日：2005-11-17

Applicant: Hideki Higashitani

Inventor： Hideki Higashitani

IPC: H05K1/11 ,  H05K1/00 ,  B05D5/12

CPC classification number: H05K1/0271 ,  H01L21/563 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  H05K3/0052 ,  H05K2201/09136 ,  H05K2201/09909 ,  H05K2201/2009 ,  H05K2203/0278 ,  H05K2203/1105 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A wiring board which includes a product portion configured with at least one layer of electrically insulating base, a wiring pattern formed on the surface or inner portion of the electrically insulating base, and a wiring protection layer which is formed on the surface of the board and has an opening. Warping over the entire wiring board can be reduced since this wiring board has a warp-correcting portion warped in a direction different from that of the product portion.

Abstract translation: 一种布线基板，其具备：形成有至少一层电绝缘基体的产品部，形成在所述电绝缘基材的表面或内部的布线图案，以及形成在所述基板的表面上的布线保护层，以及 有一个开口。 由于该布线板具有与产品部分不同的方向翘曲的翘曲矫正部，所以可以减少整个布线板的翘曲。