公开(公告)号：HK1207700A1

公开(公告)日：2016-02-05

申请号：HK15108076

申请日：2015-08-20

Applicant: IBM

Inventor： GREINER DAN ,  JACOBI CHRISTIAN ,  SLEGEL TIMOTHY

IPC: G06F20060101

Abstract: A TRANSACTION BEGIN instruction begins execution of a transaction and includes a general register save mask having bits, that when set, indicate registers to be saved in the event the transaction is aborted. At the beginning of the transaction, contents of the registers are saved in memory not accessible to the program, and if the transaction is aborted, the saved contents are copied to the registers.

公开(公告)号：HK1207447A1

公开(公告)日：2016-01-29

申请号：HK15108093

申请日：2015-08-20

Applicant: IBM

Inventor： GREINER DAN ,  JACOBI CHRISTIAN ,  SLEGEL TIMOTHY ,  ROGERS ROBERT

IPC: G06F20060101

Abstract: Execution of instructions in a transactional environment is selectively controlled. A TRANSACTION BEGIN instruction initiates a transaction and includes controls that selectively indicate whether certain types of instructions are permitted to execute within the transaction. The controls include one or more of an allow access register modification control and an allow floating point operation control.

公开(公告)号：HK1207444A1

公开(公告)日：2016-01-29

申请号：HK15108075

申请日：2015-08-20

Applicant: IBM

Inventor： GREINER DAN ,  SLEGEL TIMOTHY ,  JACOBI CHRISTIAN

IPC: G06F20060101

公开(公告)号：ZA201400730B

公开(公告)日：2015-10-28

申请号：ZA201400730

申请日：2014-01-30

Applicant: IBM

Inventor： COPELAND REID ,  GAINEY JR CHARLES ,  SCHWARZ ERIC MARK ,  MITRAN MARCEL ,  SLEGEL TIMOTHY ,  CARLOUGH STEVEN

Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.

公开(公告)号：CA2940905A1

公开(公告)日：2015-10-01

申请号：CA2940905

申请日：2015-03-19

Applicant: IBM

Inventor： GREINER DAN ,  FARRELL MARK ,  OSISEK DAMIAN LEO ,  SCHMIDT DONALD WILLIAM ,  BUSABA FADI YUSUF ,  KUBALA JEFFREY PAUL ,  BRADBURY JONATHAN DAVID ,  HELLER LISA CRANTON ,  SLEGEL TIMOTHY ,  GAINEY CHARLES JR ,  JACOBI CHRISTIAN

IPC: G06F9/46 ,  G06F9/50

Abstract: Embodiments relate to dynamic enablement of multithreading. According to an aspect, a computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread, and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. The computer system also includes a multithreading facility configured to control the configuration to perform a method. The method includes executing in the primary thread in the ST mode, an MT mode setting instruction. A number of threads requested is obtained from a location specified by the MT mode setting instruction. Based on determining that the number of threads requested indicates multiple threads, the MT mode is enabled to execute the multiple threads including the primary thread and the one or more secondary threads.

公开(公告)号：MX2015009458A

公开(公告)日：2015-09-24

申请号：MX2015009458

申请日：2013-12-06

Applicant: IBM

Inventor： SLEGEL TIMOTHY ,  SCHWARZ ERIC MARK ,  BRADBURY JONATHAN DAVID ,  GSCHWIND MICHAEL KARL

IPC: G06F17/16

Abstract: Se facilita el manejo de la excepción del vector. Se ejecuta una instrucción vectorial que opera en uno o más elementos de un registro del vector. Cuando una excepción se encuentra durante la ejecución de la instrucción, se proporciona un código de excepción del vector, que indica una posición dentro del registro del vector que causó la excepción. El código de excepción del vector también incluye una razón para la excepción.

公开(公告)号：DE112013002040T5

公开(公告)日：2015-04-16

申请号：DE112013002040

申请日：2013-05-21

Applicant: IBM

Inventor： JACOBI CHRISTIAN ,  GREINER DAN ,  SLEGEL TIMOTHY

IPC: G06F9/30 ,  G06F9/38

Abstract: Eine Transaktion, die in einer Datenverarbeitungsumgebung ausgeführt wird, endet vor dem Abschluss, d. h. die Ausführung wird abgebrochen. Entsprechend einer Abbruchausführung wird ein transaktionsgebundener Ausführungsmodus einer Hardware-CPU verlassen, und eines oder mehrere der Folgenden wird ausgeführt: Zurückspeichern von ausgewählten Registern; Festschreiben von nicht transaktionsgebundenen Speicherungen bei Abbruch; Verzweigung auf einen durch ein Transaktionsabbruch-Programmstatuswort angegebenen Speicherort; Setzen eines Bedingungscodes und/oder Abbruchcodes; und/oder Beibehalten von Diagnoseinformationen.

公开(公告)号：MX2014015290A

公开(公告)日：2015-04-10

申请号：MX2014015290

申请日：2012-11-22

Applicant: IBM

Inventor： GREINER DAN ,  SLEGEL TIMOTHY ,  MITRAN MARCEL ,  JACOBI CHRISTIAN

IPC: G06F11/07

Abstract: Cuando se presenta el aborto de una transacción en un sistema de computadora, se toma una determinación en cuanto a si la información de diagnóstico va a ser almacenada en uno más bloquees de diagnóstico de transacción (TDB). Hay diferentes tipos de bloques de diagnóstico de transacción para aceptar información de diagnóstico de transacción para aceptar información de diagnóstico dependiendo del tipo de aborto y otras consideraciones. Como ejemplos, hay un TDB especifico del programa en el cual la información es almacenada si se provee una dirección de TDB válida en una instrucción de comienzo de transacción; un TDB de interrupción del programa que es almacenado cuando el programa es abortado debido a una interrupción y un TDB de intercepción del programa, que es almacenado cuando un aborto da como resultado una intercepción.

公开(公告)号：GB2517876A

公开(公告)日：2015-03-04

申请号：GB201500043

申请日：2013-05-20

Applicant: IBM

Inventor： PRASKY BRIAN ROBERT ,  VASILEVSKIY ALEXANDER ,  BONANNO JAMES JOSEPH ,  SIU JORAN ,  MITRAN MARCEL ,  SLEGEL TIMOTHY

IPC: G06F9/38 ,  G06F9/30

Abstract: Embodiments relate to branch prediction preloading. An aspect includes a system for branch prediction preloading. The system includes an instruction cache and branch target buffer (BTB) coupled to a processing circuit, the processing circuit configured to perform a method. The method includes fetching a plurality of instructions in an instruction stream from the instruction cache, and decoding a branch prediction preload instruction in the instruction stream. An address of a predicted branch instruction is determined based on the branch prediction preload instruction. A predicted target address is determined based on the branch prediction preload instruction. A mask field is identified in the branch prediction preload instruction, and a branch instruction length is determined based on the mask field. Based on executing the branch prediction preload instruction, the BTB is preloaded with the address of the predicted branch instruction, the branch instruction length, the branch type, and the predicted target address.

公开(公告)号：GB2513079B

公开(公告)日：2015-02-04

申请号：GB201414236

申请日：2013-05-21

Applicant: IBM

Inventor： GREINER DAN ,  JACOBI CHRISTIAN ,  SLEGEL TIMOTHY

IPC: G06F9/38 ,  G06F9/30