公开(公告)号：EP0847089A1

公开(公告)日：1998-06-10

申请号：EP96830614.2

申请日：1996-12-09

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Ravanelli, Enrico Maria ,  Pozzoni, Massimo ,  Pedrazzini, Giorgio ,  Ricotti, Giulio

IPC: H01L27/088 ,  H01L27/02

CPC classification number: H01L27/0248 ,  H01L27/088

Abstract: The method described is applied to an integrated circuit formed on a substrate (10) of p-type material having at least one region (11) of n-type material with junction insulation, first electrical contact means (20,21) on the frontal surface of the substrate, second electrical contact means (14,14') on the n-type region (11) and third electrical contact means (8) on the back of the substrate connected to a reference (ground) terminal of the integrated circuit. To avoid current in the substrate due to the conduction of parasitic bipolar transistors in certain operating conditions of the integrated circuit, the method provides for monitoring the potential of the second contact means (14,14') to detect if this potential departs from the (ground) potential of the reference terminal by an amount greater than a predetermined threshold value. If this occurs the first contact means (20,21) are taken to the potential of the second contact means (14,14'), otherwise they are held at the (ground)potential of the reference terminal. A device and an integrated circuit which utilise the method are also described.

Abstract translation: 所描述的方法被施加到与形成于具有n型材料中的至少一个区域（11），且结绝缘，第一电接触装置（20,21）上的头的p型材料的基片（10）的集成电路 在n型区域（11）和第三电接触装置的基板，第二电接触器件（14,14“）的表面（8）上连接到所述集成电路的基准（接地）端子的基板的背面 ， 为了避免在基片的电流由于寄生双极晶体管的集成电路中，所述方法提供了用于监测所述第二接触装置（14,14“）的电势的某些操作条件的导通来检测，如果该电势从出发（ 地）通过在量高于预定阈值的参考端子的电势。 如果发生此第一接触装置（20,21）被带到第二接触装置（14,14“）的电位，否则，这些都在参考端子的（接地）电势保持。 因此，一个装置和集成电路，其利用该方法进行了描述。

公开(公告)号：EP0845847A1

公开(公告)日：1998-06-03

申请号：EP96830602.7

申请日：1996-11-29

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Colombo, Paolo

IPC: H02H9/04

CPC classification number: H01L27/0251 ,  H01L27/0266

Abstract: Device for protection against electrostatic discharges on the terminals of a MOS integrated circuit and characterized in that it comprises a first (N1,N2) and a second circuit branches (R1,N3,R2;T,R) between the terminal to be protected (VPP PAD) and ground with the first circuit branch comprising a first (N1) and a second field-effect transistors and having respective gate terminals connected respectively to the terminal and to a first end of a first resistance (R2;R) included in the second circuit branch and having a second end connected to ground.
The second circuit branch comprises a third field-effect transistor (N3) having its gate terminal connected to ground and a second resistance (R1) inserted between the third transistor (N3) and the terminal to be protected.

Abstract translation: 用于在MOS集成电路的端子上防止静电放电的装置，其特征在于，它包括在待保护的端子之间的第一（N1，N2）和第二电路分支（R1，N3，R2; T，R） VPP PAD）并且接地，其中第一电路支路包括第一（N1）和第二场效应晶体管，并且具有相应的栅极端子分别连接到端子和第一电阻（R2; R）的第一端。 第二电路分支并具有连接到地的第二端。 第二电路分支包括其栅极端子连接到地的第三场效应晶体管（N3）和插在第三晶体管（N3）和被保护端子之间的第二电阻（R1）。

公开(公告)号：EP0845784A1

公开(公告)日：1998-06-03

申请号：EP96830598.7

申请日：1996-11-27

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Villa, Corrado ,  Defendi, Marco ,  Bettini, Luigi

IPC: G11C8/00

CPC classification number: G11C8/18

Abstract: The invention relates to a method and a circuit for generating a pulse synchronization signal (ATD) in order to control the reading phase of memorycells in semiconductor integrated, electronic memory devices. The pulse signal (ATD) is generated upon sensing a change in logic state on at least one of a plurality of address input terminals (PAD) of the memory cells to also generate an equalization signal (EQLZ) for a sense amplifier.
The logic state of said pulse signal (ATD) is re-acknowledged by a fed-back response having a predetermined delay and being generated upon reception of a corresponding signal to said equalization signal (EQLZ). To this aim, a re-acknowledge circuit portion (15) is provided which is input a corresponding signal to the equalization signal (EQLZ) and feedback connected to the output node (12) to drive the discharging of the node (12) with a predetermined delay from the reception of the input signal.

Abstract translation: 本发明涉及一种用于产生脉冲同步信号（ATD）的方法和电路，以便控制半导体集成的电子存储器件中存储单元的读取相位。 在感测存储器单元的多个地址输入端（PAD）中的至少一个上的逻辑状态的变化时产生脉冲信号（ATD），以生成用于读出放大器的均衡信号（EQLZ）。 所述脉冲信号（ATD）的逻辑状态由具有预定延迟的反馈响应重新确认，并且在接收到所述均衡信号（EQLZ）的相应信号时产生。 为此目的，提供了一个重新确认电路部分（15），其向均衡信号（EQLZ）输入相应的信号，并且连接到输出节点（12）的反馈以使得节点（12）的放电以 从接收输入信号的预定延迟。

公开(公告)号：EP0575688B1

公开(公告)日：1998-05-27

申请号：EP92830552.3

申请日：1992-10-01

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Ghio, Emilio Giambattista ,  Meroni, Giuseppe ,  Re, Danilo ,  Baldi, Livio

IPC: H01L27/112 ,  H01L21/8246

CPC classification number: H01L27/11266 ,  H01L27/112

公开(公告)号：EP0843402A1

公开(公告)日：1998-05-20

申请号：EP96830581.3

申请日：1996-11-14

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Ghilardelli, Andrea ,  Mulatti, Jacopo ,  Branchetti, Maurizio

IPC: H02M3/07

CPC classification number: H02M3/073

Abstract: A charge pump comprises a plurality of stages (S1,S2,S3',S4') connected in series between a reference potential and an output terminal (O) of the charge pump. The plurality of stages comprises a first group of stages (S1,S2), proximate to the reference potential, and a second group of stages (S3',S4') proximate to the output terminal of the charge pump. Each stage of the first group comprising a pass-transistor (M1) with first and second terminals respectively connected to an input and an output of the stage, and a first capacitor (CL) with a first plate connected to the output of the stage and a second plate driven by a digital signal (B,D) switching between the reference voltage and a positive voltage (VDD); each stage of the second group comprising a junction diode (D) having a first electrode connected to an input of the stage and a second electrode connected to an output of the stage, and a second capacitor (CL') having a first plate connected to the output of the stage and a second plate driven by a digital signal (B',D') switching between the reference voltage and the voltage supply.

Abstract translation: 电荷泵包括串联连接在电荷泵的参考电位和输出端（O）之间的多个级（S1，S2，S3'，S4'）。 多个级包括靠近参考电位的第一级级（S1，S2）和靠近电荷泵的输出端的第二组级（S3'，S4'）。 第一组的每个级包括具有第一和第二端子的传输晶体管（M1），第一和第二端子分别连接到级的输入和输出端，第一电容器（CL）具有连接到级的输出的第一板， 由数字信号（B，D）驱动的第二板，在参考电压和正电压（VDD）之间切换; 第二组的每个级包括具有连接到级的输入的第一电极和连接到级的输出的第二电极的结二极管（D）和具有连接到级的输出的第二电容器（CL'），第二电容器 该级的输出和由在基准电压和电压源之间切换的数字信号（B'，D'）驱动的第二板。

公开(公告)号：EP0837574A1

公开(公告)日：1998-04-22

申请号：EP97410092.7

申请日：1997-08-26

Applicant: SGS-THOMSON MICROELECTRONICS S.A. ,  SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Roche, Franck ,  Tonella, Maurizio

IPC: H04H1/00

CPC classification number: H04H20/22 ,  H04H2201/13

Abstract: L'invention concerne un procédé de sélection de fréquence d'un récepteur RDS, comprenant les étapes consistant à surveiller le niveau du signal reçu pour une station écoutée et, lorsque le niveau du signal devient mauvais, à sélectionner, parmi un groupe de fréquences alternatives stockées dans une table, la fréquence qui fournit le niveau de signal maximal pour la station sélectionnée. Le procédé comprend en outre l'étape consistant, même si le niveau du signal reçu pour la station écoutée est bon, à sélectionner régulièrement (206) une fréquence successive de la table afin de mesurer le niveau du signal reçu correspondant, cette sélection s'effectuant temporairement et de manière suffisamment brève pour ne pas perturber de manière audible le signal reçu pour la station écoutée.

Abstract translation: 该方法涉及监视接收信号的电平。 可以根据接收到的信号电平从存储在表中的一组频率中选择替代的调谐频率。 即使接收到的信号电平质量好，也可以定期选择来自表格的连续频率，以测量对应的接收信号电平。 该选择是暂时的并且足够短以至于不干扰接收信号的可听到的质量。 当信号电平恶化时，按照信号强度降低的顺序选择连续的频率，并用于数据传输。

公开(公告)号：EP0834897A1

公开(公告)日：1998-04-08

申请号：EP96830509.4

申请日：1996-10-04

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Baldi, Livio ,  Marangon, Maria Santina

IPC: H01J9/02 ,  H01J1/30

CPC classification number: H01J9/025 ,  H01J1/3042

Abstract: The microtips (14) of charge emitting material, which define the cathode of the flat FED screen and face the grid of the screen, are tubular and have portions (16) with a small radius of curvature. The microtips (14) are obtained by forming openings (10) in the dielectric layer (6) separating the cathode connection layer (3, 5) from the grid layer (8), depositing a conducting material layer (11, 12) to cover the walls of the openings, and anisotropically etching the layer of conducting material to remove it, i.a., from the upper edge of the portion covering the walls, so as to form inwardly-inclined surfaces (15) with emitting tips (16). Subsequently, the portions of the dielectric layer surrounding the microtips are removed (18).

Abstract translation: 限定平面FED屏幕的阴极并且面对屏幕的栅格的电荷发射材料的微尖端（14）是管状的并且具有小的曲率半径的部分（16）。 通过在将阴极连接层（3,5）与栅格层（8）分离的电介质层（6）中形成开口（10），沉积导电材料层（11,12）来覆盖微芯片（14） 开口的壁，并且各向异性地蚀刻导电材料层以从覆盖壁的部分的上边缘除去它，从而形成具有发射尖端（16）的向内倾斜的表面（15）。 随后，去除围绕微尖头的电介质层的部分（18）。

公开(公告)号：EP0833453A1

公开(公告)日：1998-04-01

申请号：EP96830490.7

申请日：1996-09-30

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Kramer, Alan, c/o SGS-Thomson Microelec. S.r.l. ,  Canegallo, Roberto ,  Chinosi, Mauro ,  Gozzini, Giovanni ,  Leong, Philip, c/o SGS-Thomson Microelec. S.r.l. ,  Rolandi, Pier Luigi ,  Sabatini, Marco, c/o SGS-Thomson Microelec. S.r.l.

IPC: H03M1/74

CPC classification number: H03M1/74

Abstract: The present invention relates to a digital-to-analog converter having a plurality of inputs (B0,B1,B2,B3) for digital signals and an output (OUT) for an analog signal, and comprising a current amplification circuit (AMP) having an input (ND) and an output coupled to the converter output; and a plurality of floating gate MOS transistors (M01, M11, M21, M31) corresponding to the plurality of converter inputs and having their source terminals coupled together and to a first reference (GND) of potential, drain terminals coupled together and to the input (ND) of the amplification circuit (AMP), and control terminals coupleable, under control from the inputs of the plurality, to different references (GND,VCC) of potential having selected fixed values.

Abstract translation: 数模转换器本发明涉及一种数模转换器，具有用于数字信号的多个输入（B0，B1，B2，B3）和用于模拟信号的输出（OUT），并且包括具有电流放大电路（AMP）的电流放大电路 输入（ND）和耦合到转换器输出的输出; 以及与多个转换器输入对应并且其源极端子耦合在一起的多个浮置栅极MOS晶体管（M01，M11，M21，M31）和耦合在一起的电位漏极端子的第一参考（GND） （ND），以及控制端子，可在多个输入端的控制下耦合到具有所选择的固定值的不同参考电压（GND，VCC）。

公开(公告)号：EP0833347A1

公开(公告)日：1998-04-01

申请号：EP96830498.0

申请日：1996-09-30

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Kramer, Alan c/o SGS-Thomson Microelectr. S.r.l. ,  Canegallo, Roberto ,  Chinosi, Mauro ,  Gozzini, Giovanni ,  Rolandi, Pier Luigi ,  Sabatini, Marco

IPC: G11C27/00

CPC classification number: G11C27/005

Abstract: The programmable reference voltage source (1) includes a nonvolatile memory cell (2), the floating-gate region (3) of which stores electric charges determining a memorized threshold value. The drain terminal (4) of the cell is biased at a constant voltage (D r ), and the source terminal (14) is connected to a constant-current source (21) and to the inverting input of an operational amplifier (21) having the noninverting input connected to a reference voltage (V r ) and the output (10) connected to the gate terminal (8) of the cell (2). By defining the threshold of the cell (2) as the gate voltage (measured with respect to ground) capable of causing the cell (2) to be flown by the current (I s ) set by the current source (22), the output voltage (V o ) of the operational amplifier (21) equals the threshold and may be used as a programmable reference in analog memories.

Abstract translation: 可编程参考电压源（1）包括非易失性存储单元（2），其浮动栅极区域（3）存储确定存储的阈值的电荷。 电池的漏极端子（4）以恒定电压（Dr）被偏置，并且源极端子（14）连接到恒流源（21）和与运算放大器（21）的反相输入端相连， 连接到参考电压（Vr）的非反相输入和连接到单元（2）的栅极端子（8）的输出（10）。 通过将电池（2）的阈值定义为能够使电池（2）由电流源（22）设定的电流（Is）流动的栅极电压（相对于地测量），输出电压 运算放大器（21）的电压（Vo）等于阈值，并且可以用作模拟存储器中的可编程参考。

公开(公告)号：EP0829965A1

公开(公告)日：1998-03-18

申请号：EP96830471.7

申请日：1996-09-17

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l. ,  MAGNETI MARELLI S.p.A.

Inventor： Poletto, Vanni ,  Poma, Alberto ,  Morelli, Marco

IPC: H03K17/945 ,  G01F23/00

CPC classification number: H03K17/945 ,  G01F23/0069 ,  G01F23/0084

Abstract: A circuit for controlling the reserve lamp (LAMP) of a vehicle's fuel level indicator instrument (STR). The circuit uses a switch (SW1) controlled by an extremely asymmetric clock signal (CLK) periodically to switch, for a very short time, the signal (Rj) provided by the level sensor (SENS) towards a comparator (CMP) operable to compare this signal (Rj) with a threshold value (Rth) for the purpose of determining the state of the reserve lamp (LAMP).

Abstract translation: 一种用于控制车辆燃料液位指示器（STR）的储备灯（LAMP）的电路。 该电路周期性地使用由非常不对称的时钟信号（CLK）控制的开关（SW1），以在非常短的时间内将由电平传感器（SENS）提供的信号（Rj）朝向可操作以比较的比较器（CMP） 该信号（Rj）具有用于确定储备灯（LAMP）的状态的阈值（Rth）。