公开(公告)号：KR100397176B1

公开(公告)日：2003-09-06

申请号：KR1020010045070

申请日：2001-07-26

Applicant: 삼성전자주식회사

Inventor： 조민수 ,  김동준 ,  류의열 ,  김대근 ,  김용희 ,  하상록 ,  김광복 ,  남정림 ,  김경현

IPC: H01L21/3105

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L29/66553

Abstract: Disclosed is a method of planarizing a non-volatile memory device. After forming a floating gate structure on a cell area of a semiconductor substrate, a conductive layer, a hard mask layer and a first insulating layer are sequentially formed on the entire surface of the resultant structure. After removing the first insulating layer of the cell area to leave a first insulating layer pattern only on the peripheral circuit area, the hard mask layer of the cell area is removed. A second insulating layer is formed on the conductive layer and the insulating layer pattern to increase the height of the insulating layer on the peripheral circuit area. The second insulating layer and the first insulating layer pattern are removed until the floating gate structure is exposed, thereby planarizing the cell area and the peripheral circuit area. The conductive layer is patterned to form wordlines on both sidewalls of the floating gate structure and simultaneously, to form a gate of a logic device on the peripheral circuit area. When a CMP process for forming the wordline is carried out, the excessive polishing of the cell area adjacent to the peripheral circuit area can be prevented.

Abstract translation: 公开了一种平坦化非易失性存储器件的方法。 在半导体衬底的单元区域上形成浮置栅极结构之后，在所得结构的整个表面上依次形成导电层，硬掩模层和第一绝缘层。 在去除单元区域的第一绝缘层以仅在外围电路区域上留下第一绝缘层图案之后，去除单元区域的硬掩模层。 在导电层和绝缘层图案上形成第二绝缘层以增加外围电路区域上的绝缘层的高度。 去除第二绝缘层和第一绝缘层图案，直到浮置栅极结构被暴露，由此使单元区域和外围电路区域平坦化。 将导电层图案化以在浮置栅极结构的两个侧壁上形成字线，并同时在外围电路区域上形成逻辑器件的栅极。 当执行用于形成字线的CMP工艺时，可以防止与外围电路区域相邻的单元区域的过度抛光。