公开(公告)号：KR1020110135086A

公开(公告)日：2011-12-16

申请号：KR1020100054812

申请日：2010-06-10

Applicant: 삼성전자주식회사

Inventor： 임하진 ,  도진호 ,  김원홍 ,  송문균 ,  주대권

IPC: H01L21/336 ,  H01L21/318 ,  H01L27/092

CPC classification number: H01L21/823857 ,  H01L21/28202 ,  H01L29/518

Abstract: PURPOSE: A semiconductor device and a method of manufacturing the same are provided to suppress the increase of a leakage current and a threshold voltage in an NMOS area while reducing carrier mobility in a PMOS area. CONSTITUTION: In a semiconductor device and a method of manufacturing the same, a gate insulting layer including a high-k dielectric material in a substrate having an NMOS area(I) and a PMOS area(II). A first gate conductive film is formed on the gate insulating layer. A second gate conductive film is formed on the gate insulating layer and the first gate conductive film. First and second gate structures(172,174) are formed in the NMOS and PMOS regions by patterning first and the second gate conductive film and gate insulating layer.

Abstract translation: 目的：提供半导体器件及其制造方法，以抑制NMOS区域中的漏电流和阈值电压的增加，同时降低PMOS区域中的载流子迁移率。 构成：在半导体器件及其制造方法中，在具有NMOS区域（I）和PMOS区域（II）的衬底中包括高k电介质材料的栅极绝缘层。 在栅极绝缘层上形成第一栅极导电膜。 在栅极绝缘层和第一栅极导电膜上形成第二栅极导电膜。 通过图案化第一栅极导电膜和栅极绝缘层，在NMOS和PMOS区域中形成第一和第二栅极结构（172,174）。

公开(公告)号：KR102264257B1

公开(公告)日：2021-06-14

申请号：KR1020140193004

申请日：2014-12-30

Applicant: 삼성전자주식회사

Inventor： 이민주 ,  김원홍 ,  송문균 ,  유동수 ,  최수정

IPC: H01L21/205 ,  H01L21/02

公开(公告)号：KR101900042B1

公开(公告)日：2018-09-18

申请号：KR1020120049765

申请日：2012-05-10

Applicant: 삼성전자주식회사

Inventor： 원석준 ,  오영묵 ,  송문균 ,  송민우 ,  조남규

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/6656 ,  H01L21/28008 ,  H01L21/31111 ,  H01L21/762 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/092 ,  H01L29/6653 ,  H01L29/66553

Abstract: 반도체소자가제공된다. 기판의제 1 영역상에차례로적층된제 1 게이트유전층, 제 1 하부게이트전극, 및제 1 상부게이트전극이제공된다. 기판의제 2 영역상에차례로적층된제 2 게이트유전층, 제 2 하부게이트전극, 및제 2 상부게이트전극이제공된다. 제 1 상부게이트전극의측벽을차례로덮는제 1 스페이서및 제 3 스페이서가제공되고, 제 2 상부게이트전극의측벽을차례로덮는제 2 스페이서및 제 4 스페이서가제공된다. 상기제 1 하부게이트전극의측벽은상기제 3 스페이서와접촉한다.

公开(公告)号：KR1020160007115A

公开(公告)日：2016-01-20

申请号：KR1020140087307

申请日：2014-07-11

Applicant: 삼성전자주식회사

Inventor： 원석준 ,  김원홍 ,  송문균

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/324 ,  H01L21/31

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/321 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: 반도체소자의제조방법이제공된다. 상기반도체소자의제조방법은기판상에트렌치를포함하는층간절연막을형성하고, 상기트렌치내에제1 고유전율(high-k)막을형성하고, 상기고유전율막상에제1 금속층을형성하고, 상기제1 금속층이노출된상태에서, 상기제1 고유전율막및 상기제1 금속층을제1 온도로제1 열처리를하여상기제1 금속층에포함된산소를상기제1 고유전율막에확산시켜제2 고유전율막을형성하고, 상기제1 금속층이노출된상태에서, 상기제2 고유전율막을, 상기제1 온도보다높은피크(peak) 온도를가지는제2 열처리를하고, 상기제1 금속층상에제2 금속층을형성하는것을포함한다.

Abstract translation: 提供一种制造半导体器件的方法。 制造半导体器件的方法包括：在衬底上形成包括沟槽的层间绝缘膜; 在沟槽中形成第一高介电常数（high-k）膜; 在高介电常数膜上形成第一金属层; 在第一高介电常数薄膜和第一金属层的第一温度下进行第一热处理，第一金属层暴露，以通过将包含在第一金属层中的氧扩散到第一高介电常数形成第二高介电常数膜 电影; 在第二高介电常数膜上，在第一金属层暴露的情况下，在高于第一温度的峰值温度下进行第二热处理; 以及在所述第一金属层上形成第二金属层。

公开(公告)号：KR1020120133652A

公开(公告)日：2012-12-11

申请号：KR1020110052395

申请日：2011-05-31

Applicant: 삼성전자주식회사

Inventor： 송문균 ,  임하진 ,  박문한 ,  도진호

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L21/823412 ,  H01L21/823807 ,  H01L29/1025

Abstract: PURPOSE: A manufacturing method for a semiconductor device is provided to improve current characteristics by simultaneously performing a fluorine ion injection process and a high pressure thermal process for a channel region of the semiconductor device. CONSTITUTION: Provided is a substrate(100) including an NMOS(N-channel metal oxide semiconductor) region and a PMOS(P-channel metal oxide semiconductor) region. Fluorine(F) ion is injected into an upper side of the substrate. A first gate electrode of the NMOS region and a second gate electrode of the PMOS region are formed on the substrate. A source region and a drain region(107) are formed within respective adjacent substrates on both sides of a first gate electrode and a second gate electrode. High pressure heat treatment is performed using non-oxidative gas on the upper side of the substrate. [Reference numerals] (AA) NMOS region; (BB) PMOS region

Abstract translation: 目的：提供半导体器件的制造方法，通过同时对半导体器件的沟道区域进行氟离子注入工艺和高压热处理来提高电流特性。 构成：提供了包括NMOS（N沟道金属氧化物半导体）区域和PMOS（P沟道金属氧化物半导体）区域的衬底（100）。 将氟（F）离子注入基板的上侧。 在衬底上形成NMOS区的第一栅电极和PMOS区的第二栅电极。 在第一栅电极和第二栅电极的两侧上的各个相邻衬底内形成源极区和漏极区（107）。 在基板的上侧使用非氧化性气体进行高压热处理。 （AA）NMOS区域; （BB）PMOS区

公开(公告)号：KR1020120107762A

公开(公告)日：2012-10-04

申请号：KR1020110025474

申请日：2011-03-22

Applicant: 삼성전자주식회사

Inventor： 도진호 ,  임하진 ,  김원홍 ,  홍경일 ,  송문균

IPC: H01L21/8228 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L21/823462 ,  H01L21/26506 ,  H01L21/28185 ,  H01L21/2822 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848 ,  H01L21/823857

Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to control germanium oxide on the top of a silicon-germanium layer. CONSTITUTION: A substrate including a NMOS(n-channel metal oxide semiconductor) region and a PMOS(p-channel metal oxide semiconductor) region is prepared. A silicon-germanium layer is formed on the PMOS region(S1). Nitrogen is inserted into the top of the silicon-germanium layer(S2). A first gate insulating layer(S3) is formed in the NMOS region and the PMOS region. Nitrogen implantation is performed before the formation of the first gate insulating layer. [Reference numerals] (S1) Formation of a SiGe layer on a PMOS region; (S2) Insertion of nitrogen into the top of the SiGe layer; (S3) Formation of a gate insulating layer

Abstract translation: 目的：提供一种用于制造半导体器件的方法，以控制硅 - 锗层顶部的氧化锗。 构成：制备包括NMOS（n沟道金属氧化物半导体）区和PMOS（p沟道金属氧化物半导体）区的衬底。 在PMOS区（S1）上形成硅 - 锗层。 将氮气插入硅 - 锗层（S2）的顶部。 在NMOS区域和PMOS区域中形成第一栅极绝缘层（S3）。 在形成第一栅极绝缘层之前进行氮注入。 （S1）在PMOS区域上形成SiGe层; （S2）将氮气插入到SiGe层的顶部; （S3）形成栅极绝缘层

公开(公告)号：KR1020120035017A

公开(公告)日：2012-04-13

申请号：KR1020100096470

申请日：2010-10-04

Applicant: 삼성전자주식회사

Inventor： 임하진 ,  박문한 ,  김은곤 ,  도진호 ,  김원홍 ,  송문균 ,  주대권

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L21/28123 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/32134 ,  H01L21/32139 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477

Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to protect a gate insulation layer by using a hard mask and an etch stop layer. CONSTITUTION: A gate insulation layer(120) including high dielectric materials is formed on a substrate. An etch stop layer(130) is formed on the gate insulation layer. A metal layer is formed on the etch stop layer. A hard mask(155) including amorphous silicon is formed on the metal layer. A metal film pattern(142) is formed by patterning the metal layer using the hard mask as an etch mask.

Abstract translation: 目的：提供一种用于制造半导体器件的方法，以通过使用硬掩模和蚀刻停止层来保护栅极绝缘层。 构成：在基板上形成包括高介电材料的栅绝缘层（120）。 在栅极绝缘层上形成蚀刻停止层（130）。 在蚀刻停止层上形成金属层。 在金属层上形成包括非晶硅的硬掩模（155）。 通过使用硬掩模作为蚀刻掩模对金属层进行图案化来形成金属膜图案（142）。

公开(公告)号：KR1020110134696A

公开(公告)日：2011-12-15

申请号：KR1020100054420

申请日：2010-06-09

Applicant: 삼성전자주식회사

Inventor： 도진호 ,  임하진 ,  김원홍 ,  정회성 ,  송문균 ,  주대권

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L21/02236 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02271 ,  H01L21/02532 ,  H01L21/28194 ,  H01L21/28211 ,  H01L29/51 ,  H01L29/513 ,  H01L29/4232

Abstract: PURPOSE: A fabricating method of a semiconductor device is provided to improve the reliability of a whole semiconductor device by forming a first gate insulating film having improved a TDDB(Time Dependent Dielectric Breakdown) property. CONSTITUTION: In a fabricating method of a semiconductor device, an epitaxial layer is grown up on a semiconductor substrate(S1010). A capping layer is formed on the epitaxial layer(S1020). A first gate insulating layer is formed by oxidizing the capping layer under oxygen. A second gate insulating layer is formed in the first gate insulating film(S1040).

Abstract translation: 目的：提供半导体器件的制造方法，以通过形成具有改进的TDDB（时间依赖介电击穿）特性的第一栅极绝缘膜来提高整个半导体器件的可靠性。 构成：在半导体器件的制造方法中，在半导体衬底上生长外延层（S1010）。 在外延层上形成覆盖层（S1020）。 通过在氧气下氧化封盖层形成第一栅极绝缘层。 在第一栅极绝缘膜中形成第二栅极绝缘层（S1040）。