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公开(公告)号：KR1020140104843A
公开(公告)日：2014-08-29
申请号：KR1020130018836
申请日：2013-02-21
Applicant: 삼성전자주식회사
Inventor： 신영민
IPC: H03K17/687 , H03K19/00 , H03K3/3565
CPC classification number: H03K3/012 , H03K3/3565 , H03K17/164 , H03K19/0016
Abstract: Disclosed in the present invention are a power gating circuit especially using a Schmitt trigger circuit, a semiconductor integrated circuit, and a system. The power gating circuit uses the Schmitt trigger circuit connected between a first power line and a second power line and detecting a voltage level of the second power line to connect or separate the first power line and the second power line. The power gating circuit is connected between a first ground power line and a second ground power line, and uses the Schmitt trigger circuit detecting a voltage level of the second ground power line to connect or separate the first ground power line and the second ground power line.
Abstract translation: 在本发明中公开了一种电源门控电路，特别是使用施密特触发电路，半导体集成电路和系统。 电源门控电路使用连接在第一电力线和第二电力线之间的施密特触发电路，并且检测第二电力线的电压电平以连接或分离第一电力线和第二电力线。 电源门控电路连接在第一接地电力线和第二接地电力线之间，并且使用施密特触发电路检测第二接地电力线的电压电平来连接或分离第一接地电力线和第二接地电力线 。
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公开(公告)号：KR1020130125039A
公开(公告)日：2013-11-18
申请号：KR1020120048455
申请日：2012-05-08
Applicant: 삼성전자주식회사
CPC classification number: G06F12/0811 , G06F1/3234 , G06F1/3275 , G06F12/0833 , G06F12/084 , G06F2212/1028 , G06F2212/283 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D50/20
Abstract: A multi-CPU system includes a first CPU including a first L2 cache controller connected to one or more first CPU cores, a second CPU including a second L2 cache controller connected to one or more second CPU cores and the first CPU and the second CPU physically share one or more parts of a L2 cache integrated with the second CPU.
Abstract translation: 多CPU系统包括：第一CPU，包括连接到一个或多个第一CPU核心的第一L2高速缓存控制器;第二CPU，包括连接到一个或多个第二CPU内核的第二L2高速缓存控制器，以及物理上的第一CPU和第二CPU 共享与第二个CPU集成的L2缓存的一个或多个部分。
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25.发明授权
公开(公告)号：KR100813273B1
公开(公告)日：2008-03-13
申请号：KR1020070001159
申请日：2007-01-04
Applicant: 삼성전자주식회사 , 재단법인서울대학교산학협력재단
IPC: H01L21/027
CPC classification number: G03F7/00 , G03F1/22 , G03F9/7053 , G03F9/7076 , G03F1/60
Abstract: A mask for use in an LIGA(Lithographie Galvanofomung Abformung) process, a method for manufacturing the same, and a method for manufacturing a micro structure using the LIGA process are provided to reduce an alignment error with respect to photoresist layers by inserting an aligning pin into aligning pin holes on the entire photoresist layers. A substrate(120) for a structure, a photoresist layer(152) comprised of a plating hole(155) and an aligning pin hole(157) formed on a position corresponding to the plating hole, an aligning pin capable of being inserted into the aligning pin hole are manufactured. Processes for laminating the photoresist layer on the substrate for a structure and forming a plating layer by plating a metal in the plating hole are repeated by the number of the photoresist layers. The alignment between the laminated photoresist layer and a photoresist layer to be laminated is accomplished by inserting the aligning pin into the aligning pin hole on the entire laminated photoresist layer.
Abstract translation: 提供了用于LIGA（Lithographie Galvanofomung Abformung）工艺的掩模，其制造方法和使用LIGA工艺制造微结构的方法，以通过将对准销插入来减少相对于光致抗蚀剂层的对准误差 在整个光致抗蚀剂层上对准针孔。 一种用于结构的衬底（120），由形成在与所述电镀孔相对应的位置上的电镀孔（155）和对准销孔（157）构成的光致抗蚀剂层（152），能够插入到所述电镀孔 制造对准销孔。 通过光致抗蚀剂层的数量重复用于层压用于结构的光致抗蚀剂层和通过在电镀孔中镀覆金属形成镀层的工艺。 层压的光致抗蚀剂层和要层压的光致抗蚀剂层之间的对准是通过将对准销插入整个层叠的光致抗蚀剂层上的对准销孔来实现的。
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Patent Agency Ranking
公开(公告)号：KR1020040037453A
公开(公告)日：2004-05-07
申请号：KR1020020065940
申请日：2002-10-28
Applicant: 삼성전자주식회사
Inventor： 신영민
IPC: G06F11/00
CPC classification number: H04L7/0008 , H03K5/26 , H04L7/0025
Abstract: PURPOSE: A clock delay detecting circuit and a method for detecting clock delay are provided to detect clock delay for an initial parameter of a clock forwarding circuit, and control reset of an external circuit. CONSTITUTION: The system comprises a master circuit, a slave circuit. The master circuit includes a clock delay detecting circuit, receives a system reset signal, and generates a reset control signal. The reset control signal responses to the clock signal and the system reset signal. The slave circuit resets the response of the reset control signal, receives output data and output clock signal, and supplies input data synchronizing by the input clock signal. The clock delay detecting signal generates the reset control signal, detects delay between the output clock signal and input click signal, and performs loading and unloading operation of the input data.
Abstract translation: 目的：提供时钟延迟检测电路和检测时钟延迟的方法，以检测时钟转发电路的初始参数的时钟延迟，并控制外部电路的复位。 构成：系统包括主电路，从电路。 主电路包括时钟延迟检测电路，接收系统复位信号，并产生复位控制信号。 复位控制信号响应于时钟信号和系统复位信号。 从电路复位复位控制信号的响应，接收输出数据和输出时钟信号，并提供与输入时钟信号同步的输入数据。 时钟延迟检测信号产生复位控制信号，检测输出时钟信号和输入点击信号之间的延迟，并执行输入数据的加载和卸载操作。
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公开(公告)号：KR1020020072658A
公开(公告)日：2002-09-18
申请号：KR1020010012604
申请日：2001-03-12
Applicant: 삼성전자주식회사
Inventor： 신영민
IPC: G11C29/00
CPC classification number: G01R31/318577
Abstract: PURPOSE: A semiconductor integrated circuit incorporating therein a plurality of local monitor circuits is provided to easily and rapidly measure a change of on-chip process with respect to an operation speed. CONSTITUTION: A semiconductor integrated circuit(100) includes a boundary scan register(120) and a plurality of local monitor circuits(160). Each of the local monitor circuits(160) is individually assigned to a peripheral of the boundary scan register(120) and the semiconductor integrated circuit(100) in order to measure and predict an operation speed of the semiconductor integrated circuit(100) according to the change of on-chip process in a number of various local regions of the semiconductor integrated circuit(100). The operation speed of the semiconductor integrated circuit(100) is determined in consideration of a general signal delay time measured through the boundary scan register(120) and a correlation of local signal delay times respectively measured through the local monitor circuits(160).
Abstract translation: 目的：提供一种其中结合有多个局部监视器电路的半导体集成电路，用于容易且快速地测量相对于操作速度的片上处理的变化。 构成：半导体集成电路（100）包括边界扫描寄存器（120）和多个本地监视电路（160）。 每个本地监视电路（160）被分别分配给边界扫描寄存器（120）和半导体集成电路（100）的外围设备，以便测量和预测半导体集成电路（100）的操作速度，根据 在半导体集成电路（100）的多个局部区域中的片上处理的变化。 考虑到通过边界扫描寄存器（120）测量的通常的信号延迟时间和分别通过本地监视电路（160）测量的本地信号延迟时间的相关性来确定半导体集成电路（100）的操作速度。
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公开(公告)号：KR1020010087940A
公开(公告)日：2001-09-26
申请号：KR1020000011826
申请日：2000-03-09
Applicant: 삼성전자주식회사
Inventor： 신영민
IPC: G11C5/14
Abstract: PURPOSE: A circuit for switching reference voltage of a comparator is provided to prevent unnecessary current consumption of a comparator by cutting off reference voltage of the comparator in a comparison process. CONSTITUTION: A reference voltage pad(200) generates a reference voltage. A comparator(500) has an input tab connected with a pad(100). A switch circuit(300) connects the reference voltage input tab of the comparator(500) with the reference voltage pad(200). A control circuit(400) operates the switch circuit(300). The switch circuit(300) includes a unit which connects/separates the reference voltage input tab of the comparator(500) with/from the reference voltage pad(200), and a switch which connects the reference voltage input tab of the comparator(500) with the ground.
Abstract translation: 目的：提供一种用于切换比较器参考电压的电路，以便在比较过程中通过切断比较器的参考电压来防止比较器的不必要的电流消耗。 构成：参考电压焊盘（200）产生参考电压。 比较器（500）具有与焊盘（100）连接的输入接片。 开关电路（300）将比较器（500）的参考电压输入接头连接到参考电压焊盘（200）。 控制电路（400）操作开关电路（300）。 开关电路（300）包括将比较器（500）的参考电压输入引脚与参考电压焊盘（200）连接/分离的单元，以及连接比较器（500）的参考电压输入引脚 ）与地面。
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公开(公告)号：KR100176173B1
公开(公告)日：1999-04-01
申请号：KR1019950050702
申请日：1995-12-15
Applicant: 삼성전자주식회사
Inventor： 신영민
IPC: H03B19/00
Abstract: 모오스 캐페시터의 전하 충방전 시간을 최소화한 주파수 체배 회로 및 이를 이용한 오실레이터를 공개한다. 본 발명에 따른 주파수 체배 회로는 전원전압과 접지 사이에 P채널 및 N채널 모오스 캐페시터를 병렬 연결함에 의해 P채널 및 N채널 모오스 캐페시터의 특성에 따른 전하 충방전 시간의 차이를 없앨 수 있다. 오실레이터는 상기 주파수 체배 회로의 양측에 대역통과필터를 배치하고, 이 필터을 통해 노이즈를 제거하고 오프셋 전압을 고정적으로 설정함에 의해 발진 주파수의 듀티값을 안정적으로 유지하고 주파수 편차를 최소화할 수 있다는 잇점이 있다.
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公开(公告)号：KR100163905B1
公开(公告)日：1998-12-15
申请号：KR1019950031216
申请日：1995-09-21
Applicant: 삼성전자주식회사
IPC: G06F7/00
Abstract: 이 발명은 산술 논리 연산장치의 입력 강제 회로에 관한 것으로, 프로그램으로부터 제어신호를 입력받아 그에따라 적절한 제어신호를 출력하기 위한 마이크로 코드 롬과; 상기 마이크로 코드 롬의 제어신호를 입력받아, 입력받은 데이터를 이용하기에 편리한 형태로 변환하기 위한 데이터 변환부와; 상기 마이크로 코드 롬의 제어신호에 따라 상기 데이터 변환부로부터 입력되는 데이터를 처리하기 위한 산술 논리 연산장치의 입력 강제 회로와; 상기 마이크로 코드 롬의 제어신호를 입력받아, 상기 산술 논리 연산장치의 입력 강제 회로의 출력 데이터와 상기 데이터 변환부의 출력 데이터를 연산하기 위한 산술 논리 연산장치를 포함하여 구성되어, 실제 제어하려는 대상에 적합한 지원만을 해줌으로써 간단하면서 작은 면적을 차지하는 것을 특징으로 하는 산술 논리 연산장치의 입력 강제 장치에 관한 것이다.
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