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公开(公告)号：KR1020080110387A
公开(公告)日：2008-12-18
申请号：KR1020070059075
申请日：2007-06-15
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L45/06 , H01L45/1233 , H01L45/141
Abstract: A phase change memory device and a method of manufacture thereof is provided to improve the program efficiency of the phase change memory device as the contact area of a bottom electrode and phase change material pattern becomes small. A phase change memory device comprises a plurality of bottom electrodes, a plurality of isolation patterns(109), a plurality of phase change material patterns(111) and a plurality of resist patterns(113). The bottom electrodes connects the fixed regions of the semiconductor substrate through insulating layers(103, 115) formed on the semiconductor substrate(101) and are separated each other and are positioned. The isolation patterns respectively cover the partial domains of bottom electrodes corresponding to bottom electrodes. The isolation patterns are separated each other and are positioned. The phase change material pattern surrounds the side walls of the isolation patterns. The phase change material pattern is connected to the upper sides of the bottom electrodes. The resist pattern surrounds the side walls of the phase change material patterns.
Abstract translation: 提供一种相变存储器件及其制造方法，用于随着底部电极和相变材料图案的接触面积变小而提高相变存储器件的编程效率。 相变存储器件包括多个底部电极，多个隔离图案（109），多个相变材料图案（111）和多个抗蚀剂图案（113）。 底部电极通过形成在半导体衬底（101）上的绝缘层（103,115）连接半导体衬底的固定区域并彼此分离并定位。 隔离图案分别覆盖对应于底部电极的底部电极的部分域。 隔离图案彼此分离并定位。 相变材料图案围绕隔离图案的侧壁。 相变材料图案连接到底部电极的上侧。 抗蚀剂图案包围相变材料图案的侧壁。
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22.发明授权
公开(公告)号：KR100791008B1
公开(公告)日：2008-01-04
申请号：KR1020060134177
申请日：2006-12-26
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L45/144 , G11C11/5678 , G11C13/0004 , H01L27/2409 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/1675
Abstract: A phase-change memory device having a phase change material pattern shared between adjacent cells and an electronic product including the same are provided to minimize electrical interference between phase change memory cells by arranging the phase change material pattern in an oblique direction with respect to columns and rows of lower electrodes. A plurality of lower electrodes(BE) are arranged in a matrix. A plurality of phase change material patterns are connected electrically to the lower electrodes. Each of the phase change material patterns is commonly connected to two or more lower electrodes which are adjacent to each other in an oblique direction with respect to columns and rows of the lower electrodes. A gap, between the adjacent lower electrodes of the lower electrodes connected electrically to each of the phase change material patterns, is larger than a gap between the lower electrodes arranged in each of rows and a gap between the lower electrodes arranged in each column.
Abstract translation: 提供具有在相邻单元之间共享的相变材料图案和包括该相变单元的电子产品的相变存储器件，以通过相对于列倾斜方向布置相变材料图案来最小化相变存储单元之间的电干扰，并且 行下电极。 多个下电极（BE）以矩阵形式布置。 多个相变材料图案电连接到下电极。 每个相变材料图案通常连接到相对于下电极的列和行在倾斜方向上彼此相邻的两个或更多个下电极。 在与每个相变材料图案电连接的下电极的相邻下电极之间的间隙大于布置在每行中的下电极与布置在每列中的下电极之间的间隙之间的间隙。
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公开(公告)号：KR100675289B1
公开(公告)日：2007-01-29
申请号：KR1020050108797
申请日：2005-11-14
Applicant: 삼성전자주식회사
IPC: H01L27/10
Abstract: A phase change memory cell array region and its manufacturing method are provided to prevent a thermal disturbance between adjacent cells by using an amorphous ion implanted region of a phase changeable material layer as an isolation layer of the phase changeable material layer. A lower interlayer dielectric is formed on a semiconductor substrate. Conductive plugs are formed through the lower interlayer dielectric. A phase changeable material pattern(32') is formed on the lower interlayer dielectric to cover at least two conductive plugs. The phase changeable material pattern is composed of first regions for contacting the conductive plugs and a second region between the first regions. The second region has a lower thermal conductivity than that of the first region. An upper interlayer dielectric is formed thereon. Conductive patterns are formed through the upper interlayer dielectric to contact electrically predetermined portions of the first regions. The second region of the phase changeable material pattern contains predetermined ions of 5 at%.
Abstract translation: 通过使用相变材料层的非晶离子注入区域作为相变材料层的隔离层，提供相变存储单元阵列区域及其制造方法以防止相邻单元之间的热扰动。 在半导体衬底上形成下部层间电介质。 导电插塞通过下层间电介质形成。 相变材料图案（32'）形成在下层间电介质上以覆盖至少两个导电插塞。 相变材料图案由用于接触导电插塞的第一区域和第一区域之间的第二区域组成。 第二区域具有比第一区域低的导热率。 在其上形成上层间电介质。 导电图案穿过上层间电介质形成以接触第一区域的电预定部分。 相变材料图案的第二区域包含5at％的预定离子。
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公开(公告)号：KR100423906B1
公开(公告)日：2004-03-22
申请号：KR1020010047667
申请日：2001-08-08
Applicant: 삼성전자주식회사
IPC: H01L27/105
CPC classification number: H01L27/11502 , G11C11/22 , H01L27/11507 , H01L28/57
Abstract: The method of forming a ferroelectric memory device includes forming capacitor patterns over a substrate, each capacitor pattern having an adhesive assistant pattern, a lower electrode, a ferroelectric pattern, and an upper electrode. An oxygen barrier layer is formed over the substrate and is etched to expose a sidewall of the ferroelectric pattern but not a sidewall of the adhesive assistant pattern. Then, a thermal process for curing ferroelectricity of the ferroelectric pattern is performed.
Abstract translation: 形成铁电存储器件的方法包括在衬底上形成电容器图案，每个电容器图案具有粘合剂辅助图案，下电极，铁电图案和上电极。 在衬底上方形成氧阻挡层并对其进行蚀刻以暴露铁电图案的侧壁，但不暴露粘合剂辅助图案的侧壁。 然后，进行用于固化铁电图形的铁电性的热处理。
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公开(公告)号：KR1020020080908A
公开(公告)日：2002-10-26
申请号：KR1020010020766
申请日：2001-04-18
Applicant: 삼성전자주식회사
IPC: H01L27/105
CPC classification number: H01L28/65 , H01L27/10852 , H01L27/10882 , H01L28/57
Abstract: PURPOSE: An FRAM(Ferroelectric Random Access Memory) device and a method for manufacturing the same are provided to be capable of easily connecting an upper electrode to a plate line. CONSTITUTION: A cell capacitor of an FRAM device comprises a cylindrical lower electrode(132), a ferroelectric film(134), and upper electrodes(136'139') composed of double conductive layers. The lower electrode(132) is provided with a cylindrical structure having a bottom for closing sidewalls and lower portions of the cylindrical structure. The ferroelectric film(134) is provided with a liner shape faced to inner sides of the cylindrical lower electrode(132). A gap-filling film(137) is formed between the first upper electrode(136') and the second upper electrode(139') for filling a capacitor hole. The second upper electrode(139') is electrically connected to a plate line(150).
Abstract translation: 目的：提供FRAM（铁电随机存取存储器）装置及其制造方法，以便能够容易地将上电极连接到板线。 构成：FRAM器件的电池电容器包括圆柱形下电极（132），铁电体膜（134）和由双重导电层构成的上电极（136'139'）。 下电极（132）设置有具有用于封闭圆柱形结构的侧壁和下部的底部的圆柱形结构。 铁电体膜（134）具有面向圆筒形下部电极（132）的内侧的衬垫形状。 在用于填充电容器孔的第一上电极（136'）和第二上电极（139'）之间形成间隙填充膜（137）。 第二上电极（139'）电连接到板线（150）。
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Patent Agency Ranking
公开(公告)号：KR100184450B1
公开(公告)日：1999-04-15
申请号：KR1019950042983
申请日：1995-11-22
Applicant: 삼성전자주식회사
IPC: G11B20/04
Abstract: 1. 청구범위에 기재된 발명이 속하는 기술분야
기억용량을 확장하기 위한 하드 디스크 제어장치에 관한 것이다.
2. 발명이 해결하고자하는 기술적 과제
하드디스크의 기억용량을 압축율에 따라 확장한다.
3. 발명의 해결방법의 요지
기록시 하드디스크의 최대용량보다 1/K배 압축하여 저장하고, 재생시 압축된 데이터를 신장하므로, 하드디스크의 최대용량보다 K배 더 기억용량을 확장시킨다.
4. 발명의 중요한 용도
하드디스크 제어장치에 적용한다.-
公开(公告)号：KR1019980065868A
公开(公告)日：1998-10-15
申请号：KR1019970001047
申请日：1997-01-15
Applicant: 삼성전자주식회사
IPC: H02H7/20
Abstract: 본 발명은 셋 ESD 보호 회로에 관한 것으로, 메인 파워 입력단에 연결되고, 전원단자로부터 상기 메인 파워 입력단에 입력되는 순간 고전압을 디스챠징시키는 제 1 디스챠지 수단과, 전원단자로부터 상기 메인 파워 입력단에 입력되는 상기 순간 고전압이 상기 메인 파워 입력단에 순간 입력되는 것을 방지하는 제 2 디스챠지 수단과, 전원단자로부터 소정의 전압을 입력받고, 이 전압이 일정 전압 이상이 되었을 때, 상기 제 1 디스챠지 수단을 구동시키는 디스챠지 구동회로부를 포함하여, 수천 또는 수만 볼트 이상의 전압이 순간적으로 셋에 가해졌을 때 셋을 안정적으로 보호할 수 있고, 셋의 동작 기능에 이상이 없도록 할 수 있으며, 셋 ESD의 기능을 향상시킬 수 있다.
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公开(公告)号：KR1019940011663B1
公开(公告)日：1994-12-23
申请号：KR1019920013349
申请日：1992-07-25
Applicant: 삼성전자주식회사
IPC: G06F11/16
CPC classification number: H03M13/151
Abstract: The n error correction system uses n-1 error correction system. The error correction method comprises steps of obtaining n error values and locations; obtaining 2n-1 syndromes from them (100); converting 2n-2 syndromes from 2n-1 new syndromes (200); correcting errors using new syndromes (300); repeating above steps until n-1 errors are corrected (400); and calculating actual error value and final error location (600,700). The error correction system comprises a syndrome conversion unit; an error correction unit; a count unit; an actual error value and location calculating unit.
Abstract translation: n纠错系统采用n-1纠错系统。 误差校正方法包括获得n个误差值和位置的步骤; 从他们获得2n-1个综合征（100）; 从2n-1个新综合征转换2n-2个综合征（200）; 使用新的综合征纠正错误（300）; 重复上述步骤直到纠正n-1个错误（400）; 并计算实际误差值和最终误差位置（600,700）。 误差校正系统包括校正子转换单元; 纠错单元; 计数单位 一个实际的误差值和位置计算单元。
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公开(公告)号：KR1019940001147B1
公开(公告)日：1994-02-14
申请号：KR1019910004391
申请日：1991-03-20
Applicant: 삼성전자주식회사
CPC classification number: G06F7/726 , G06F2207/7209 , G11B20/1833 , H03M13/033 , H03M13/151
Abstract: The operating circuit on GF (2m) using a Galois field GF (2m/2) includes converting means for converting an element expressed by a base on GF (2m) into an element expressed by a base on GF (2m/2), operating means for perfoming an operation of the element expressed as the base on the GF (2m/2) onto GF (2m/2), and inversely-converting means for inversely converting the element expressed as the base on the operated GF (2m/2) onto the element expressed by the base on GF (2m) to perform the corresponding method, thereby simplifying the circuit and reducing the speed.
Abstract translation: 使用伽罗瓦域GF（2m / 2）的GF（2m）上的工作电路包括转换装置，用于将GF（2m）上的基数表示的元素转换为由GF（2m / 2）上的基数表示的元素， 用于将在GF（2m / 2）上作为GF（2m / 2）的基础表示的元素的操作的装置用于在所操作的GF（2m / 2）上逆向转换表示为基础的元素的逆转换装置 ）到由GF（2m）上的基座表示的元件上以执行相应的方法，从而简化电路并降低速度。
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公开(公告)号：KR1019930018578A
公开(公告)日：1993-09-22
申请号：KR1019920002220
申请日：1992-02-14
Applicant: 삼성전자주식회사
IPC: G06F3/06
Abstract: 본 발명의 디지탈데이타 저장시스템은 데이타 저장 또는 돌출하기 위한 데이타 저장수단; 상기 데이타 저장수단으로 부터의 디지탈신호를 처리하는 디지탈신호 처리수단; 상기 데이타 저장수단과 상기 디지탈신호 처리수단사이에서 데이타의 드라이빙, 버퍼링을 위한 인터페이스수단; 상기 디지탈신호 처리수단을 제어하기 위한 시스템 제어 마이크로 컴퓨터; 상기 디지탈신호 처리수단과 상호 연결되고 데이타의 저장이 가능한 리드와 라이트가 가능한 메모리수단; 상기 메모리수단에 저장된 데이타를 모니터할 수 있는 주 컴퓨터; 및 상기 메모리수단과 주 컴퓨터 사이의 데이타 인터페이스를 위한 인터페이스부로 구성된 것을 특징으로 한다.
따라서, 속도가 빠르고, 무게가 가벼우며, 메모리의 용량이 커지면 가격이 저렴해진다.
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