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公开(公告)号：KR101653569B1
公开(公告)日：2016-09-02
申请号：KR1020090081976
申请日：2009-09-01
Applicant: 삼성전자주식회사 , 오보닉스, 아이엔씨.
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L45/141 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/124 , H01L45/144
Abstract: 본발명은, 낮은전압에서동작하고낮은전력소모특성을가지는상변화물질을포함하는비휘발성메모리소자를제공한다. 본발명의일실시예에따른비휘발성메모리소자는, 하부전극, 하부전극상에전기적으로연결되도록위치하고, InSbTe의조성을가지는상변화물질을포함하는상변화물질층, 및상변화물질층상에전기적으로연결되도록위치하는상부전극을포함한다. 여기에서, 0.001≤X≤0.3 이고, 0.001≤Y≤0.8 이고, 0.001≤Z≤0.7 이고, X+Y+Z=1 이다.
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公开(公告)号：KR1020110044535A
公开(公告)日：2011-04-29
申请号：KR1020090101262
申请日：2009-10-23
Applicant: 삼성전자주식회사
CPC classification number: G11C13/004 , G11C11/5678 , G11C13/0004 , G11C13/0069
Abstract: PURPOSE: A nonvolatile memory device and a storage system having the same, a driving method of the nonvolatile memory device are provided to improve the reliability of a reading operation by including a data read circuit. CONSTITUTION: In a nonvolatile memory device and a storage system having the same, a driving method of the nonvolatile memory device, a memory cell array comprises a plurality of nonvolatile memory cells. Each nonvolatile memory cell has a resistor. The resistor is one of a plurality of first resistors. . A temperature compensation circuit(17) comprises at least one reference cell(110). Each reference cell has a resistor. . The resistor is one of a plurality of second resistors A data read circuit supplies a compensating current to a sensing node. The data read circuit comprises a compensation unit and a sense amp unit The amount of compensation current is changed according to the resistance of a reference cell.
Abstract translation: 目的：提供一种非易失性存储器件和具有该非易失性存储器件的存储系统，该非易失性存储器件的驱动方法是通过包括数据读取电路来提高读取操作的可靠性。 构成：在非易失性存储器件和具有该非易失性存储器件的存储系统中，非易失性存储器件的驱动方法，存储单元阵列包括多个非易失性存储器单元。 每个非易失性存储单元都有一个电阻。 电阻器是多个第一电阻器之一。 。 温度补偿电路（17）包括至少一个参考单元（110）。 每个参考单元都有一个电阻。 。 电阻器是多个第二电阻器A之一。数据读取电路向感测节点提供补偿电流。 数据读取电路包括补偿单元和读出放大单元。补偿电流量根据参考单元的电阻而改变。
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公开(公告)号：KR1020090036769A
公开(公告)日：2009-04-15
申请号：KR1020070102004
申请日：2007-10-10
Applicant: 삼성전자주식회사
CPC classification number: G11C13/0004 , G11C13/004 , G11C13/0069
Abstract: A method for operating a phase change random access memory and the phase change random access memory operated thereby are provided to cool the data storage element which is programmed by using the Pettier effect. The first write current(IP1) is applied to the data storage element for the designated time. The first write current is the impulse current having the predetermined size. The direction of the first write current is the negative direction or the positive direction. The first write current is applied to the phase change material film(G) for the predetermined time. The temperature of the phase transformation region is instantaneously increased over the phase transformation temperature. The phase transformation region is phase-transformed into the amorphous state by the first write current. The phase change material film is programmed to the reset status.
Abstract translation: 提供一种用于操作相变随机存取存储器和由其操作的相变随机存取存储器的方法以冷却通过使用Pettier效应编程的数据存储元件。 在指定时间内，第一个写入电流（IP1）被应用于数据存储元件。 第一写入电流是具有预定尺寸的脉冲电流。 第一个写入电流的方向是负方向或正方向。 将第一写入电流施加到相变材料膜（G）预定时间。 在相变温度下相变温度瞬时增加。 相变区域通过第一写入电流被相变成非晶态。 相变材料膜被编程为复位状态。
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4.发明授权
公开(公告)号：KR100791008B1
公开(公告)日：2008-01-04
申请号：KR1020060134177
申请日：2006-12-26
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L45/144 , G11C11/5678 , G11C13/0004 , H01L27/2409 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/1675
Abstract: A phase-change memory device having a phase change material pattern shared between adjacent cells and an electronic product including the same are provided to minimize electrical interference between phase change memory cells by arranging the phase change material pattern in an oblique direction with respect to columns and rows of lower electrodes. A plurality of lower electrodes(BE) are arranged in a matrix. A plurality of phase change material patterns are connected electrically to the lower electrodes. Each of the phase change material patterns is commonly connected to two or more lower electrodes which are adjacent to each other in an oblique direction with respect to columns and rows of the lower electrodes. A gap, between the adjacent lower electrodes of the lower electrodes connected electrically to each of the phase change material patterns, is larger than a gap between the lower electrodes arranged in each of rows and a gap between the lower electrodes arranged in each column.
Abstract translation: 提供具有在相邻单元之间共享的相变材料图案和包括该相变单元的电子产品的相变存储器件，以通过相对于列倾斜方向布置相变材料图案来最小化相变存储单元之间的电干扰，并且 行下电极。 多个下电极（BE）以矩阵形式布置。 多个相变材料图案电连接到下电极。 每个相变材料图案通常连接到相对于下电极的列和行在倾斜方向上彼此相邻的两个或更多个下电极。 在与每个相变材料图案电连接的下电极的相邻下电极之间的间隙大于布置在每行中的下电极与布置在每列中的下电极之间的间隙之间的间隙。
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公开(公告)号：KR1020070076360A
公开(公告)日：2007-07-24
申请号：KR1020060051782
申请日：2006-06-09
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/1666
Abstract: A method for forming a phase changeable structure is provided to make a phase change layer pattern have a lateral surface with almost no defects by including a phase change structure with a switch function such that the phase change structure is composed of a lower electrode, an upper electrode and a phase change layer pattern between the lower and the upper electrodes and includes chalcogenide. An insulation layer(100) is formed which has an opening filled with a lower electrode(200). A phase change layer(300) is formed on the insulation layer, electrically coming in contact with the lower electrode and including chalcogenide. The chalcogenide can include germanium, antimony and tellurium. A metal-including conductive layer is formed on the phase change layer. The conductive layer is etched by using a first material including a first component with fluorine to form an upper electrode(410). The phase change layer is etched by using a second material without chlorine to form a phase change layer pattern between the upper electrode and the lower electrode.
Abstract translation: 提供一种用于形成相变结构的方法，通过包括具有开关功能的相变结构使得相变结构由下电极，上层 电极和下电极和上电极之间的相变层图案，并且包括硫族化物。 形成绝缘层（100），其具有填充有下电极（200）的开口。 在绝缘层上形成相变层（300），与下电极电接触并包括硫族化物。 硫族化物可以包括锗，锑和碲。 在相变层上形成含有金属的导电层。 通过使用包括具有氟的第一组分的第一材料来蚀刻导电层以形成上电极（410）。 通过使用没有氯的第二材料来蚀刻相变层，以在上电极和下电极之间形成相变层图案。
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Patent Agency Ranking
公开(公告)号：KR1020070063856A
公开(公告)日：2007-06-20
申请号：KR1020050124119
申请日：2005-12-15
Applicant: 삼성전자주식회사
Inventor： 배준수
IPC: H04N7/08
CPC classification number: H04H60/12 , H04H60/72 , H04H2201/11 , H04J13/00 , H04N7/08 , H04N21/235 , H04N21/236
Abstract: A DMB(Digital Multimedia Broadcasting) system and a method for outputting additional information are provided to prevent a user from being bored or uncomfortable even in a weak field state in case that a DMB signal is poorly received. An additional information generator(208) generates additional information, and inputs the additional information into a predetermined channel to transmit the additional information. A first channel data generator generates channel data of the predetermined channel, and inserts the additional data into the generated channel data to output the resultant data. A multiplexer(210) multiplexes channel data received from the first channel data generator and channel data received from a second channel data generator, and outputs the multiplexed channel data.
Abstract translation: 提供了一种DMB（数字多媒体广播）系统和一种用于输出附加信息的方法，以防止用户在DMB信号接收不良的情况下即使在弱场状态下也无聊或不舒服。 附加信息生成器（208）产生附加信息，并将附加信息输入到预定信道中以发送附加信息。 第一通道数据发生器产生预定通道的通道数据，并将附加数据插入到所生成的通道数据中以输出结果数据。 多路复用器（210）将从第一通道数据发生器接收的通道数据和从第二通道数据发生器接收的通道数据进行复用，并输出复用的通道数据。
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公开(公告)号：KR1020050023706A
公开(公告)日：2005-03-10
申请号：KR1020030061090
申请日：2003-09-02
Applicant: 삼성전자주식회사
Inventor： 배준수
IPC: H01L21/66
CPC classification number: G01R31/3004 , G01R31/2894 , G01R31/31718
Abstract: PURPOSE: EDS(Electrical Die Sorting) test system is provided to reduce the time and the man power required to measurement by monitoring a voltage in real time with a voltage measuring device. CONSTITUTION: EDS test system includes a prober system, a power supply unit and a voltage measuring device. The power supply unit is located within the prober system. The voltage measuring device measures a voltage of the voltage supply unit. The voltage measuring device comprises a measuring unit and a plurality of display units. The measuring unit is connected with voltage check terminals of the voltage supply unit and a common ground terminal. The plurality of display units connected electrically with the measuring unit monitors the respective voltage of the voltage check terminal by measuring in real time.
Abstract translation: 目的：提供EDS（电气模具分选）测试系统，通过电压测量装置实时监测电压，减少测量所需的时间和人力。 规定：EDS测试系统包括探测系统，电源单元和电压测量设备。 电源单元位于探测系统内。 电压测量装置测量电压供应单元的电压。 电压测量装置包括测量单元和多个显示单元。 测量单元与电源单元的电压检查端子和公共接地端子相连。 与测量单元电连接的多个显示单元通过实时测量来监视电压检查端子的各自的电压。
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公开(公告)号：KR101390337B1
公开(公告)日：2014-04-29
申请号：KR1020070093170
申请日：2007-09-13
Applicant: 삼성전자주식회사
CPC classification number: G11C13/0061 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C16/32 , G11C2013/009 , G11C2013/0092 , Y10S977/754
Abstract: 여기에 제공되는 멀티-레벨 상변환 메모리 장치의 프로그램 방법은 선택된 메모리 셀에 프로그램될 멀티-레벨 데이터를 입력받는 단계와; 그리고 상기 입력된 멀티-레벨 데이터에 따라 상기 선택된 메모리 셀에 프로그램 신호를 인가하는 단계를 포함하며, 상기 프로그램 신호의 상승 시간은 상기 프로그램 신호의 하강 시간보다 길게 설정된다.
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公开(公告)号：KR101311499B1
公开(公告)日：2013-09-25
申请号：KR1020070085043
申请日：2007-08-23
Applicant: 삼성전자주식회사
IPC: G11C13/02
CPC classification number: G11C13/0069 , G11C11/5678 , G11C13/0004 , G11C2013/0078 , G11C2013/0092
Abstract: 본 발명은 가변 저항 메모리 장치의 프로그램 방법에 관한 것이다. 상기 가변 저항 메모리 장치는 멀티 상태(multi_state)를 갖는 메모리 셀; 및 상기 메모리 셀을 멀티 상태 중 어느 하나로 프로그램하기 위한 프로그램 펄스를 제공하는 쓰기 드라이버를 포함한다. 상기 가변 저항 메모리 장치의 프로그램 방법은 상기 메모리 셀로 제 1 프로그램 펄스를 인가하는 단계; 및 상기 메모리 셀이 중간 상태(intermediate state)로 프로그램되는 경우에, 상기 메모리 셀로 제 2 프로그램 펄스를 인가하는 단계를 포함한다. 여기에서, 상기 제 1 프로그램 펄스가 리셋 펄스인 경우에, 상기 리셋 펄스는 오버 프로그램 펄스(이하, 오버 리셋 펄스라 함)인 것을 특징으로 한다. 본 발명에 의하면, 저항 드리프트 마진을 개선할 수 있을 뿐만 아니라, 충분한 읽기 마진을 확보할 수 있다.
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公开(公告)号：KR1020090084218A
公开(公告)日：2009-08-05
申请号：KR1020080010262
申请日：2008-01-31
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L45/06 , G11C13/0004 , H01L45/141
Abstract: A variable resistance memory device is provided to suppress the resistance drift phenomenon by suppressing the volume expansion in the state change. The first conductive pattern(112) is formed on a substrate(100). A resistance alteration pattern(124) is formed on the first conductive pattern. The first stress buffer pattern(122) contacts with the resistance alteration pattern. The second conductive pattern(132) is formed on the resistance alteration pattern. The second stress buffer pattern contacts with the side of the resistance alteration pattern or a part among the lower surface of the resistance alteration pattern.
Abstract translation: 提供了一种可变电阻存储器件，通过抑制状态变化中的体积膨胀来抑制电阻漂移现象。 第一导电图案（112）形成在基板（100）上。 电阻变化图案（124）形成在第一导电图案上。 第一应力缓冲图案（122）与电阻变化图案接触。 第二导电图案（132）形成在电阻变化图案上。 第二应力缓冲图案与电阻变化图案的一侧或电阻变化图案的下表面中的一部分接触。
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