-
公开(公告)号：KR1020100104372A
公开(公告)日：2010-09-29
申请号：KR1020090022747
申请日：2009-03-17
Applicant: 삼성전자주식회사
CPC classification number: H01L23/49541 , H01L23/49575 , H01L23/50 , H01L23/535 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L2224/05554 , H01L2224/32145 , H01L2224/32245 , H01L2224/48095 , H01L2224/48145 , H01L2224/48147 , H01L2224/48247 , H01L2224/4911 , H01L2224/49175 , H01L2224/73265 , H01L2224/83191 , H01L2225/0651 , H01L2225/06562 , H01L2924/00014 , H01L2924/01005 , H01L2924/01027 , H01L2924/01075 , H01L2924/12042 , H01L2924/181 , H01L23/48 , H01L23/12 , H01L2924/00 , H01L2224/48175 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
Abstract: PURPOSE: A semiconductor package is provided to reduce a mounting area of a substrate by reducing the number of semiconductor packages connected to a controller. CONSTITUTION: A semiconductor package includes a semiconductor chip, a lead, a first pin group(20), and a second pin group(20'). The lead is connected to the semiconductor chip and is exposed to the outside. The first pin group is exposed in one direction of the semiconductor chip and is connected to the first channel line of the controller. The second pin group is exposed in other direction of the semiconductor chip and is connected to the second channel line of the controller.
Abstract translation: 目的：提供半导体封装，通过减少连接到控制器的半导体封装的数量来减少衬底的安装面积。 构成：半导体封装包括半导体芯片，引线，第一引脚组（20）和第二引脚组（20'）。 引线连接到半导体芯片并暴露在外部。 第一引脚组暴露在半导体芯片的一个方向上，并连接到控制器的第一通道线。 第二引脚组在半导体芯片的另一方向上露出并连接到控制器的第二通道线。
-
公开(公告)号：KR100800478B1
公开(公告)日：2008-02-04
申请号：KR1020060067099
申请日：2006-07-18
Applicant: 삼성전자주식회사
IPC: H01L23/12
CPC classification number: H01L23/3128 , H01L21/565 , H01L21/568 , H01L23/49811 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L2224/16225 , H01L2224/16235 , H01L2224/16237 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/48228 , H01L2224/73204 , H01L2224/73265 , H01L2225/0651 , H01L2225/06568 , H01L2225/1023 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/07802 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/0401 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: 적층형 반도체 패키지 및 그의 제조방법을 제공한다. 상기 적층형 반도체 패키지는 하부 단위 패키지 및 상부 단위 패키지를 구비한다. 상기 하부 단위 패키지는 기판과 상기 기판의 상면 상에 배치된 반도체 칩을 구비한다. 상기 기판의 상면 상에 범프가 배치되고, 상기 반도체 칩을 덮는 보호층이 배치되되, 상기 보호층은 상기 범프의 일부를 노출시키는 비아홀을 갖는다. 상기 상부 단위 패키지는 상기 보호층 상에 배치되고, 하면 상에 내부 연결 솔더볼을 구비한다. 상기 내부 연결 솔더볼은 상기 비아홀 내에 삽입되어 상기 범프에 접속한다.
-
公开(公告)号：KR1020080007893A
公开(公告)日：2008-01-23
申请号：KR1020060067099
申请日：2006-07-18
Applicant: 삼성전자주식회사
IPC: H01L23/12
CPC classification number: H01L23/3128 , H01L21/565 , H01L21/568 , H01L23/49811 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L2224/16225 , H01L2224/16235 , H01L2224/16237 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/48228 , H01L2224/73204 , H01L2224/73265 , H01L2225/0651 , H01L2225/06568 , H01L2225/1023 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/07802 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/0401 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: A stack type semiconductor package and a method for fabricating the same are provided to obtain reliable connection between stacked unit packages by inserting an internal connection solder ball of an upper unit package into a via hole of a protective layer of a lower unit package. A semiconductor chip(150) is arranged on a substrate(100). A bump(120) is arranged on an upper surface of the substrate. A lower unit package includes a protective layer(170) which is formed to cover a protective layer(170). The protective layer includes a via hole(170a) for exposing a part of the bump. An upper unit package is arranged on the protective layer. An internal connection solder ball(190_2) is formed on the lower surface of the upper unit package. The internal connection solder ball is inserted into the via hole to be connected to the bump.
Abstract translation: 提供堆叠型半导体封装及其制造方法，以通过将上单元封装的内部连接焊球插入到下单元封装的保护层的通孔中来获得层叠单元封装之间的可靠连接。 半导体芯片（150）布置在基板（100）上。 凸起（120）布置在基板的上表面上。 下单元封装包括形成为覆盖保护层（170）的保护层（170）。 保护层包括用于暴露凸块的一部分的通孔（170a）。 上部单元封装布置在保护层上。 内部连接焊球（190_2）形成在上单元封装的下表面上。 内部连接焊球插入到通孔中以连接到凸块。
-
公开(公告)号：KR1020140047931A
公开(公告)日：2014-04-23
申请号：KR1020120114303
申请日：2012-10-15
Applicant: 삼성전자주식회사
Inventor： 염근대
CPC classification number: H01L23/50 , H01L23/481 , H01L23/49811 , H01L23/49827 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/32225 , H01L2224/73253 , H01L2225/06513 , H01L2225/06541 , H01L2225/1023 , H01L2225/107 , H01L2924/15311 , H01L2924/15331 , H01L2924/18161
Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes an interposer, a first semiconductor package which is electrically connected to the lower surface of the interposer, and at least two second semiconductor packages which are electrically connected to the upper surface of the interposer and are separated from each other in a direction parallel to the upper surface of the interposer.
Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括内插器，电连接到插入器的下表面的第一半导体封装以及至少两个第二半导体封装，它们电连接到插入器的上表面并沿着方向 平行于插入件的上表面。
-
公开(公告)号：KR1020130075251A
公开(公告)日：2013-07-05
申请号：KR1020110143554
申请日：2011-12-27
Applicant: 삼성전자주식회사
CPC classification number: H01L25/105 , H01L21/563 , H01L23/13 , H01L23/3128 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L24/16 , H01L24/48 , H01L24/73 , H01L2224/131 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/06568 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/15311 , H01L2924/15321 , H01L2924/181 , H01L2924/18161 , H01L2924/3511 , H01L2924/00012 , H01L2924/00 , H01L2924/014 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: PURPOSE: A semiconductor package including an interposer composed of a plurality of segments is provided to reduce thermal stress applied to the interposer by forming the interposer with the segments which are separately arranged. CONSTITUTION: A semiconductor chip (30) is formed on a substrate (10). An interposer (20) is arranged on the coplanar part of the substrate to surround the semiconductor chip. The interposer includes a plurality of segments (20-1 to 20-4). The segments are arranged with a quadrilateral shape on the coplanar part. An encapsulant is filled in a space between the interposer and the substrate.
Abstract translation: 目的：提供一种包括由多个段组成的插入件的半导体封装件，以通过将插入件与单独布置的段形成来降低施加到插入件的热应力。 构成：在基板（10）上形成半导体芯片（30）。 在衬底的共面部分上布置有插入件（20），以围绕半导体芯片。 插入器包括多个段（20-1至20-4）。 这些段在共面部分上以四边形形状排列。 封装剂填充在插入件和基板之间的空间中。
-
Patent Agency Ranking
公开(公告)号：KR1020110136297A
公开(公告)日：2011-12-21
申请号：KR1020100056189
申请日：2010-06-14
Applicant: 삼성전자주식회사
IPC: H01L23/12
CPC classification number: H01L25/03 , H01L23/3121 , H01L23/481 , H01L24/05 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/92 , H01L25/0657 , H01L2224/04042 , H01L2224/05009 , H01L2224/05554 , H01L2224/32145 , H01L2224/45139 , H01L2224/48145 , H01L2224/48227 , H01L2224/9202 , H01L2225/06506 , H01L2225/0651 , H01L2225/06541 , H01L2225/06562 , H01L2225/06565 , H01L2924/00011 , H01L2924/00014 , H01L2924/01079 , H01L2924/181 , H01L2924/3512 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012 , H01L2924/01049
Abstract: PURPOSE: A stacked semiconductor package is provided to make a single module of two chips with a penetration electrode, thereby improving reliability of a product by significantly increasing the stiffness of chip. CONSTITUTION: An encapsulating material(1) protects a first penetration electrode module(10), a second penetration electrode module(20), and a signal transmission medium(4). A substrate(2) supports the first penetration electrode module and the second penetration electrode module. The substrate comprises a substrate core(2b), a pattern layer(3), an upper protection layer(2a), and a lower protection layer(2c). The pattern layer is electrically connected to the signal transmission medium. The upper protection layer and lower protection layer protect a part of the pattern layer and the substrate core by covering the same.
Abstract translation: 目的：提供堆叠的半导体封装以制造具有穿透电极的两个芯片的单个模块，从而通过显着增加芯片的刚度来提高产品的可靠性。 构成：密封材料（1）保护第一穿透电极模块（10），第二穿透电极模块（20）和信号传输介质（4）。 基板（2）支撑第一穿透电极模块和第二穿透电极模块。 基板包括基板芯（2b），图案层（3），上保护层（2a）和下保护层（2c）。 图形层电连接到信号传输介质。 上保护层和下保护层通过覆盖图案层和衬底芯保护一部分。
-
公开(公告)号：KR1020100134354A
公开(公告)日：2010-12-23
申请号：KR1020090052942
申请日：2009-06-15
Applicant: 삼성전자주식회사
CPC classification number: H01L23/3128 , H01L23/3121 , H01L23/4985 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L2224/0554 , H01L2224/05553 , H01L2224/05554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2224/48227 , H01L2224/49171 , H01L2224/73207 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562 , H01L2225/06593 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/10161 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/00012 , H01L2924/00 , H01L2224/05599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/0555 , H01L2224/0556
Abstract: PURPOSE: A semiconductor package, a stacked module, a card, and an electronic system are provided to reduce the footprint of a semiconductor package by interposing a supporting unit adjusting sizes under a first semiconductor chip. CONSTITUTION: A substrate(110) includes a core board(102), a first resin layer(104), and a second resin layer(106). A first electrode finger(116) and a second electrode finger(118) are formed in the first resin layer. A plurality of first semiconductor chips(140a to 140h) is in electrical connection with the substrate. A supporting unit(130) is arranged between the substrate and the lowermost semiconductor chip using an adhesive(132).
Abstract translation: 目的：提供半导体封装，堆叠模块，卡和电子系统，以通过在第一半导体芯片下方调整尺寸的支撑单元来减小半导体封装的占地面积。 构成：基板（110）包括芯板（102），第一树脂层（104）和第二树脂层（106）。 第一电极指（116）和第二电极指（118）形成在第一树脂层中。 多个第一半导体芯片（140a〜140h）与基板电连接。 支撑单元（130）使用粘合剂（132）布置在基板和最下半导体芯片之间。
-
公开(公告)号：KR1020080112011A
公开(公告)日：2008-12-24
申请号：KR1020070060686
申请日：2007-06-20
Applicant: 삼성전자주식회사
CPC classification number: H01L23/49558 , H01L23/16 , H01L23/3107 , H01L2225/1029 , H01L2924/0002 , H01L2924/3511 , H01L2924/00
Abstract: A semiconductor package including a thermal stress absorbent member is provided to improve fatigue life preventing exfoliation or crack generation of a solder land and influencing second level reliability of a semiconductor package by preparing a thermal stress absorbent member. Semiconductor packages(110,120) comprises a semiconductor chip(125), an encapsulating material(128), lead portions(310, 320), a thermal stress absorbent member(700). The encapsulating material surrounds the semiconductor chip. The lead portion is exposed to outside. The thermal stress absorbent member absorbs the thermal stress of the semiconductor chip or the encapsulating material in order to be delivered to the lead portion.
Abstract translation: 提供一种包括热应力吸收件的半导体封装，以通过制备热应力吸收件来改善疲劳寿命，从而防止焊盘的剥离或裂纹产生以及影响半导体封装的第二级可靠性。 半导体封装（110,120）包括半导体芯片（125），封装材料（128），引线部分（310,320），热应力吸收部件（700）。 封装材料围绕半导体芯片。 引线部分暴露在外面。 热应力吸收部件吸收半导体芯片或封装材料的热应力，以便被输送到引线部分。
-
公开(公告)号：KR1020080020069A
公开(公告)日：2008-03-05
申请号：KR1020060082924
申请日：2006-08-30
Applicant: 삼성전자주식회사
IPC: H01L23/12
CPC classification number: H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2924/01322 , H01L2924/15311 , H01L2924/19107 , H01L2924/00012 , H01L2924/00
Abstract: A semiconductor package and a method of manufacturing the same are provided to reduce a stacked height and to improve a component yield by reducing a size of a solder ball in a POP(Package On Package) structure. A semiconductor chip group includes one or more semiconductor chips(150) which are laminated on a substrate(110). An attaching layer(155) is formed to attach the substrate and the lowest semiconductor chip of the semiconductor chip group with each other and to attach the semiconductor chips of the semiconductor chip group with each other by using a die-attaching manner. A bonding wire(170) is formed to connect electrically each of the semiconductor chips of the semiconductor chip group with a first electrode pad(131) formed on an upper surface of the substrate. A sealing part(160) is formed on the bonding wire, the semiconductor chip, and the substrate. A conductive column(180) is connected to a second electrode pad(132) to be extended to an upper surface of the sealing part.
Abstract translation: 提供一种半导体封装及其制造方法，以减少堆叠高度并通过减少POP（封装封装）结构中的焊球的尺寸来提高部件产量。 半导体芯片组包括层压在基板（110）上的一个或多个半导体芯片（150）。 形成附着层（155），以将基板和半导体芯片组的最低半导体芯片彼此连接，并且通过使用管芯连接方式将半导体芯片组的半导体芯片彼此附接。 形成接合线（170）以将半导体芯片组的每个半导体芯片与形成在基板的上表面上的第一电极焊盘（131）电连接。 在接合线，半导体芯片和基板上形成密封部（160）。 导电柱（180）连接到第二电极焊盘（132）以延伸到密封部分的上表面。
-
30.发明公开
公开(公告)号：KR1020070077686A
公开(公告)日：2007-07-27
申请号：KR1020060007403
申请日：2006-01-24
Applicant: 삼성전자주식회사
Inventor： 염근대
IPC: H01L23/28
CPC classification number: H01L2224/11 , H01L23/293 , H01L23/31 , H01L23/522 , H01L24/10
Abstract: A WLCSP(Wafer Level Chip Scale Package) and its manufacturing method are provided to improve a BLR(Board Level Reliability) by enhancing a solder bonding capability using a bump pad of an NSMD(Non Solder Mask Defined) type. A WLCSP includes a semiconductor chip, a first insulating layer, a rerouting layer, a mold resin layer, and a solder bump. The semiconductor chip(112) includes an inactive layer for covering an upper surface of a silicon substrate except chip pads of the substrate. The first insulating layer(120) is used for covering the inactive layer except the chip pads. The rerouting layer(150) is connected with the chip pads on the first insulating layer. A bump pad(152) is formed on one end portion of the rerouting layer. A mold resin layer(170) is formed on the first insulating layer to cover the rerouting layer. The mold resin layer includes an opening portion for exposing completely the bump pad to the outside. The solder bump(180) is formed on the bump pad.
Abstract translation: 提供WLCSP（晶片级芯片级封装）及其制造方法，通过使用NSMD（非焊接掩模定义）类型的凸块焊盘提高焊接接合能力来提高BLR（电路板级可靠性）。 WLCSP包括半导体芯片，第一绝缘层，重路由层，模制树脂层和焊料凸块。 半导体芯片（112）包括用于覆盖除了衬底的芯片焊盘之外的硅衬底的上表面的无效层。 第一绝缘层（120）用于覆盖除了芯片焊盘之外的非活性层。 重路由层（150）与第一绝缘层上的芯片焊盘连接。 在重路由层的一个端部上形成凸块（152）。 在第一绝缘层上形成模制树脂层（170）以覆盖重路由层。 模具树脂层包括用于将凸块焊盘完全暴露于外部的开口部分。 焊料凸块（180）形成在凸块焊盘上。
-
-
-
-
-
-
-
-
-
Search Results
34
records
(took 0.021 seconds)
