公开(公告)号：KR101901664B1

公开(公告)日：2018-10-01

申请号：KR1020120033936

申请日：2012-04-02

Applicant: 삼성전자주식회사

Inventor： 김길수 ,  오종민 ,  서성민 ,  유제민 ,  장성진

IPC: G11C17/18 ,  G11C7/10

CPC classification number: G11C17/18 ,  G11C7/14 ,  G11C17/16 ,  G11C29/789

Abstract: 본발명은퓨즈데이터리딩회로에관한것으로서, 퓨즈데이터를멀티리딩모드로리딩하는퓨즈데이터리딩회로에관한것이다. 본발명에서는, 퓨즈데이터를저장하는다수의퓨즈셀을구비하는퓨즈어레이; 퓨즈어레이의퓨즈셀에저장된퓨즈데이터를센싱하기위한센싱부; 퓨즈셀에저장된퓨즈데이터를리딩하는동작을제어하는제어부를포함하고, 제어부는퓨즈데이터리딩동작시에동작구간에따라퓨즈데이터를센싱하기위한센싱조건을서로다르게설정하여퓨즈데이터를리딩하도록제어하는퓨즈데이터리딩회로가제공된다.

公开(公告)号：KR1020140114621A

公开(公告)日：2014-09-29

申请号：KR1020130029116

申请日：2013-03-19

Applicant: 삼성전자주식회사

Inventor： 유제민 ,  김길수 ,  서성민 ,  송호영 ,  오종민 ,  황상준

IPC: G11C17/16 ,  G11C5/14

CPC classification number: G11C5/14 ,  G11C7/12 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4094 ,  G11C17/16 ,  G11C17/18

Abstract: Provided are an apparatus and a method for generating an anti-fuse voltage using DRAM internal voltage. The apparatus for generating an anti-fuse voltage comprises: a voltage selector which receives a first voltage required for a memory cell operation and converts the first voltage into a second voltage, different from the first voltage, required for an anti-fuse cell operation; and a transmission unit which is disposed apart from the voltage selector and transmits the second voltage to an anti-fuse cell. The anti-fuse cell operation includes at least one of a write operation for writing data on the anti-fuse cell or a read operation for extracting data information of the anti-fuse cell.

Abstract translation: 提供了使用DRAM内部电压产生抗熔丝电压的装置和方法。 用于产生抗熔丝电压的装置包括：电压选择器，其接收存储器单元操作所需的第一电压，并将第一电压转换为不同于反熔丝单元操作所需的第一电压的第二电压; 以及传输单元，其布置成与电压选择器分开并将第二电压传输到反熔丝单元。 反熔丝单元操作包括用于在反熔丝单元上写入数据的写入操作或用于提取反熔丝单元的数据信息的读取操作中的至少一个。

公开(公告)号：KR1020140036879A

公开(公告)日：2014-03-26

申请号：KR1020120103550

申请日：2012-09-18

Applicant: 삼성전자주식회사

Inventor： 오종민 ,  이윤영 ,  송호영 ,  김치욱

IPC: G11C29/00

CPC classification number: G11C29/838 ,  G11C29/787 ,  G11C2229/763

Abstract: Disclosed is a method for preventing the multiple activation of spare word lines when a memory cell fail of a second order or more is generated in a volatile semiconductor memory like DRAM. The method includes the steps of: reprogramming a fail address when a defect is in the repaired spare word line; and programming an additional bit of the fail address which is previously programmed. Also, the method includes the steps of: disabling the fail sensing data with the information of the additional bit when two or more fail sensing data is received; and activating the spare word line which is instructed by the fail sensing data which does not include the information of the additional bit.

Abstract translation: 本发明公开了一种在诸如DRAM的易失性半导体存储器中产生二次以上的存储单元故障时防止备用字线多次激活的方法。 该方法包括以下步骤：当缺陷处于已修复的备用字线时重新编程故障地址; 并编程预先编程的故障地址的另外一位。 此外，该方法包括以下步骤：当接收到两个或更多个故障感测数据时，使用附加位的信息禁用故障感测数据; 以及激活由不包括附加位的信息的故障检测数据指示的备用字线。

公开(公告)号：KR1020130134682A

公开(公告)日：2013-12-10

申请号：KR1020120058374

申请日：2012-05-31

Applicant: 삼성전자주식회사

Inventor： 류제민 ,  김길수 ,  오종민 ,  서성민 ,  송호영 ,  조용호

IPC: G11C17/16 ,  G11C7/10

CPC classification number: G11C17/16 ,  G11C7/1045 ,  G11C17/18 ,  G11C29/802

Abstract: A memory device includes a fuse device which includes a fuse cell array. The fuse cell array includes a first sub fuse cell array which stores first data related to the operation condition of the fuse device and a second sub fuse cell array which stores second data related to the operation condition of the memory device.

Abstract translation: 一种存储器件包括一个熔丝器件，它包括熔丝单元阵列。 熔丝单元阵列包括第一子熔丝单元阵列，其存储与熔丝器件的操作条件相关的第一数据，以及存储与存储器件的操作条件相关的第二数据的第二子熔丝单元阵列。

公开(公告)号：KR1020040071962A

公开(公告)日：2004-08-16

申请号：KR1020030007884

申请日：2003-02-07

Applicant: 삼성전자주식회사

Inventor： 박영렬 ,  양태호 ,  오종민 ,  문경섭

IPC: H01L21/302

Abstract: PURPOSE: A method for etching a gate electrode is provided to prevent the upper part of a gate electrode from being narrow by performing an etch process in which HBr/HeO2 gas without a Cl2 component and additionally added CF4 gas are used. CONSTITUTION: The gate electrode(21) having a deposited gate insulation layer is formed on a semiconductor substrate(13). An etch process is performed on the gate electrode by using HBr/HeO2 gas. CF4 is further added to the HBr/HeO2 gas to perform the etch process.

Abstract translation: 目的：提供一种用于蚀刻栅电极的方法，通过进行不使用Cl 2成分的HBr / HeO 2气体和附加添加的CF 4气体的蚀刻工艺来防止栅电极的上部变窄。 构成：在半导体衬底（13）上形成具有淀积栅极绝缘层的栅电极（21）。 通过使用HBr / HeO2气体在栅电极上进行蚀刻处理。 进一步向HBr / HeO2气体中加入CF 4进行蚀刻处理。