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公开(公告)号：KR1020080010600A
公开(公告)日：2008-01-31
申请号：KR1020060070826
申请日：2006-07-27
Applicant: 삼성전자주식회사
Inventor： 유현기
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L27/11519 , H01L27/11521 , H01L27/2463
Abstract: A non-volatile memory device is provided to increase driving current of a memory transistor through increase in width of an effective channel region of the memory transistor, thereby improving the performance of a memory transistor. A non-volatile memory device includes an element isolating film(12), a sensing line(SL), and a word line(WL). The element isolating film confines an active region(26). The sensing line crosses an upper part of the active region and includes a floating gate(22s) and a control gate electrode(24s). The word line is separated from the sensing line and crosses the upper part of the active region. An active region in a lower part of the word line has a width larger than an active region in a lower part of the sensing line. The width of the active region in the lower part of the word line becomes larger as the active region in the lower part of the word line becomes farther from the sensing line. The active region in the lower part of the word line includes a first region and a second region divided parallel to the word line.
Abstract translation: 提供非易失性存储器件以通过增加存储晶体管的有效沟道区的宽度来增加存储晶体管的驱动电流，从而提高存储晶体管的性能。 非易失性存储器件包括元件隔离膜（12），感测线（SL）和字线（WL）。 元件隔离膜限制有源区（26）。 感测线穿过有源区的上部并且包括浮置栅极（22s）和控制栅电极（24s）。 字线与感测线分离，并与有源区域的上部交叉。 字线下部的有源区域的宽度大于感测线下部的有效区域。 字线下部的有源区域的宽度随着字线下部的有源区域变得远离感测线而变大。 字线下部的有源区域包括平行于字线划分的第一区域和第二区域。
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公开(公告)号：KR100757326B1
公开(公告)日：2007-09-11
申请号：KR1020060099600
申请日：2006-10-13
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L27/115 , H01L27/11521 , H01L27/11524 , H01L21/823493
Abstract: A non-volatile memory device and a method for fabricating and operating the same are provided to prevent bad operation due to decrease of on current by forming a depletion channel region in a memory transistor. A sensing line(132) and a word line(130) are formed on a substrate(100), and has a tunnel oxide layer(114), a first conductive layer pattern(116a), a dielectric layer pattern(118a) and a second conductive layer pattern(120a). A depletion channel region(112) is formed under a surface of the substrate which is opposite to a bottom surface of the sensing line. An impurity region(140) is formed under the surface of the substrate which is partially by the sensing line and the word line.
Abstract translation: 提供一种非易失性存储器件及其制造和操作方法，以通过在存储晶体管中形成耗尽沟道区域来防止由于导通电流的降低导致的不良操作。 感测线（132）和字线（130）形成在基板（100）上，并且具有隧道氧化物层（114），第一导电层图案（116a），电介质层图案（118a）和 第二导电层图案（120a）。 在衬底的与感测线的底表面相对的表面下方形成耗尽沟道区（112）。 在衬底的表面下部分地由感测线和字线形成杂质区（140）。
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23.发明公开
公开(公告)号：KR1020030094497A
公开(公告)日：2003-12-12
申请号：KR1020020039425
申请日：2002-07-08
Applicant: 삼성전자주식회사
IPC: H01L21/8247
CPC classification number: H01L21/28185 , G11C16/0466 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/28282 , H01L29/4234 , H01L29/513 , H01L29/518 , H01L29/66833 , H01L29/792
Abstract: PURPOSE: A non-volatile memory cell having an SONOS(Silicon-Oxide-Nitride-Oxide-Silicon) gate structure and a manufacturing method thereof are provided to be capable of improving programming and erasing speed, reducing operation voltage, and intensifying the endurance of the memory cell. CONSTITUTION: A non-volatile memory cell(110) having an SONOS gate structure, is provided with a substrate(60) including a source and drain region(70,50), a tunneling layer(10) located at the first predetermined upper portion of the substrate, an electric charge trap layer(20) formed at the upper portion of the tunneling layer, a shielding layer(30) formed at the upper portion of the electric charge trap layer, a gate isolating layer(90) formed at the second predetermined upper portion of the substrate, and a gate(40) formed at the upper portion of the resultant structure.
Abstract translation: 目的：提供具有SONOS（硅氧化物 - 氮化物 - 氧化物 - 硅）栅极结构的非易失性存储单元及其制造方法，其能够改善编程和擦除速度，降低工作电压并增强耐久性 存储单元。 构成：具有SONOS栅极结构的非易失性存储单元（110）设置有包括源区和漏区（70,50）的衬底（60），位于第一预定上部的隧道层（10） 形成在隧道层上部的电荷阱层（20），形成在电荷陷阱层上部的屏蔽层（30），形成在栅极隔离层（90）上的栅极隔离层 基板的第二预定上部，以及形成在所得结构的上部的栅极（40）。
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公开(公告)号：KR1020030060139A
公开(公告)日：2003-07-16
申请号：KR1020020000674
申请日：2002-01-07
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247 , H01L29/788
CPC classification number: H01L27/11521 , G11C16/0433 , H01L27/115 , H01L27/11524
Abstract: PURPOSE: A split gate type non-volatile memory device and a method for manufacturing the same are provided to be capable of preventing the generation of reverse tunneling at non-select memory cells connected with a word line located near a selected memory cell by improving the structure of the device. CONSTITUTION: A non-volatile memory device is provided with a floating gate(204a) and a select gate(SL) located and spaced apart from each other on a semiconductor substrate(200), a control gate(WL) formed for partially covering the lateral portion and the upper portion of the floating gate, a tunnel oxide layer located between the control gate and the floating gate, a drain region(218d) located near the control gate in the semiconductor substrate, a cell source region(218s) located between the floating gate and the select gate in the semiconductor substrate, and a common source region(CSL) located between the select gate electrodes.
Abstract translation: 目的：提供一种分离式门型非易失性存储器件及其制造方法，以能够防止在位于选定存储单元附近的字线连接的非选择存储单元处产生反向隧穿 设备结构。 构造：非易失性存储器件在半导体衬底（200）上设置有彼此位于并间隔开的浮动栅极（204a）和选择栅极（SL），形成用于部分地覆盖 横向部分和浮动栅极的上部，位于控制栅极和浮置栅极之间的隧道氧化物层，位于半导体衬底中的控制栅极附近的漏极区域（218d），位于半导体衬底之间的电池源区域（218s） 半导体衬底中的浮置栅极和选择栅极，以及位于选择栅极之间的公共源极区域（CSL）。
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公开(公告)号：KR1020000051203A
公开(公告)日：2000-08-16
申请号：KR1019990001503
申请日：1999-01-19
Applicant: 삼성전자주식회사
Inventor： 유현기
IPC: H01L21/8239
Abstract: PURPOSE: A method for fabricating a flash memory device is provided which increases the cell density by reducing the overall cell area using a STI(Shallow Trench Isolation) process when during the process of forming a cell of an EPROM unit. CONSTITUTION: A method improves the reliability of a device by increasing the cell density, by reducing the field region area of a cell as assuring the minimum width and space of an active region by forming a flash EPROM device using a STI process. The method for fabricating a flash memory device includes the steps of: forming a trench on a semiconductor substrate(10) using STI(Shallow Trench Isolation) process; growing a gate oxide(18) on the whole surface of the inside/outside of the trench; filling the trench by depositing and etching a first polysilicon film(20) on the gate oxide, and forming an open aperture on the top; stacking a dielectric film on the whole surface of the resulted structure; depositing a silicide film(30) and a second polysilicon film(32) on the dielectric film; forming a pattern by etching from the second polysilicon film in sequence until the semiconductor substrate is revealed; forming a source/drain region on the semiconductor substrate on both sides of the pattern; and forming a contact plug on the semiconductor substrate of the source/drain region, and then forming a metal interconnection on top of the contact plug.
Abstract translation: 目的：提供一种用于制造闪速存储器件的方法，其在形成EPROM单元的单元的过程期间通过使用STI（浅沟槽隔离）工艺减小整个单元面积来增加单元密度。 构成：通过使用STI工艺形成闪存EPROM器件，通过减小电池的场区域来提高器件的可靠性，以确保有源区域的最小宽度和空间，从而提高器件的可靠性。 制造闪速存储器件的方法包括以下步骤：使用STI（浅沟槽隔离）工艺在半导体衬底（10）上形成沟槽; 在沟槽的内部/外部的整个表面上生长栅极氧化物（18）; 通过沉积和蚀刻栅极氧化物上的第一多晶硅膜（20）来填充沟槽，并且在顶部上形成开口孔; 在所得结构的整个表面上堆叠电介质膜; 在所述电介质膜上沉积硅化物膜（30）和第二多晶硅膜（32）; 通过从第二多晶硅膜依次蚀刻形成图案，直到半导体衬底露出为止; 在所述图案的两侧上的半导体衬底上形成源极/漏极区域; 以及在源极/漏极区域的半导体衬底上形成接触塞，然后在接触插塞的顶部上形成金属互连。
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Patent Agency Ranking
公开(公告)号：KR1019990008499A
公开(公告)日：1999-02-05
申请号：KR1019970030457
申请日：1997-07-01
Applicant: 삼성전자주식회사
Inventor： 유현기
IPC: H01L21/28
Abstract: 본 발명은 저 콘택저항을 가지는 반도체 장치의 제조 방법에 관한 것으로서, 특히 사진 및 식각 공정을 이용하여 반도체 기판의 층간 절연막에 콘택홀을 형성한 후에 상기 결과물에 콘택저항을 낮추기 위한 도전형 불순물을 이온 주입하는 것을 특징으로 한다. 따라서, 본 발명은 배리어 금속 형성 전 내지 후에 저농도의 도전형 불순물을 이온 주입하여 실리사이드층 밖으로 확산되는 도펀트들을 보충하므로서 안정된 콘택저항과 도펀트 분포를 확보할 수 있다.
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公开(公告)号：KR1019980052645A
公开(公告)日：1998-09-25
申请号：KR1019960071662
申请日：1996-12-24
Applicant: 삼성전자주식회사
Inventor： 유현기
Abstract: 본 발명은 심(seam) 또는 크랙 발생 등과 같은 결함 발생을 방지시킬 수 있는 층간 절연막 형성 방법에 관한 것이다. 이는, 실리콘 기판상에 소정 형상의 메탈 배선층을 형성시키는 단계와, 그 결과물의 전면에 소정 두께의 제1절연물질층을 형성시키는 단계와, 상기 제1절연물질층상에 SOG층을 형성시키는 단계와, 그리고 결과물의 전면에 절연 물질을 소정 두께로 증착시켜서 제2절연물질층을 형성시키는 단계로 이루어진 것을 층간 절연막 형성 방법에 의하여 달성된다. 유동 특성이 양호한 SOG 물질의 절연층을 형성시킴으로서 층간 절연막의 내부에 보이드 또는 심 등과 같은 결함이 발생되는 것을 방지시킴으로서 추후 공정의 진행시 누설 전류 발생 등과 같은 문제점을 해소시킬 수 있다.
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公开(公告)号：KR1020120017206A
公开(公告)日：2012-02-28
申请号：KR1020100079764
申请日：2010-08-18
Applicant: 삼성전자주식회사
CPC classification number: G11C16/06 , G11C16/0483
Abstract: PURPOSE: A nonvolatile memory cell array, a memory device, and a memory system are provided to improve reliability by reducing a disturbance property of a memory cell. CONSTITUTION: A row selector(30) selects a row of a memory cell array(10). A column selector(40) selects a column of the memory cell array. The row selector includes a common source driver(20). A read-write circuit(50) is controlled by a control circuit(70). Data stored in a buffer(60) is loaded in the read-write circuit. A voltage generating circuit(80) is controlled by the control circuit. The control circuit controls a program and a read-write operation.
Abstract translation: 目的：提供非易失性存储单元阵列，存储器件和存储器系统，以通过减小存储单元的干扰特性来提高可靠性。 构成：行选择器（30）选择一行存储单元阵列（10）。 列选择器（40）选择存储单元阵列的列。 行选择器包括公共源驱动器（20）。 读写电路（50）由控制电路（70）控制。 存储在缓冲器（60）中的数据被加载到读写电路中。 电压发生电路（80）由控制电路控制。 控制电路控制程序和读写操作。
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公开(公告)号：KR1020080074573A
公开(公告)日：2008-08-13
申请号：KR1020070013878
申请日：2007-02-09
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L27/2436 , H01L21/28273 , H01L27/2463
Abstract: A method for manufacturing a mask ROM(Read-Only-Memory) having a short channel in an on-cell region and a mask ROM manufactured by the same are provided to improve leakage current characteristic of a mask ROM device by preventing a lattice damage of a gate electrode and an interface damage. An isolation layer defining an active region is formed on a semiconductor substrate. The active region has OFF and ON active regions(102a). An OFF gate electrode(114a) having a first width is formed on the OFF active region. A gate electrode having a second width is formed on the ON active region. Before the isolation layer is formed, p-type impurity is ion-implanted to the semiconductor substrate. OFF and ON channel regions formed respectively on lower portions of the OFF and ON electrodes have same densities. Before the OFF and ON gate electrodes are formed, a gate dielectric is formed.
Abstract translation: 提供一种用于制造在单元格区域中具有短通道的掩模ROM（只读存储器）和由其制造的掩模ROM的方法，以通过防止掩模ROM器件的晶格损伤来改善掩模ROM器件的漏电流特性 栅电极和界面损坏。 在半导体衬底上形成限定有源区的隔离层。 有源区域具有OFF和ON有效区域（102a）。 在OFF有源区域上形成具有第一宽度的OFF栅电极（114a）。 具有第二宽度的栅电极形成在ON有源区上。 在形成隔离层之前，将p型杂质离子注入到半导体衬底中。 OFF和ON电极分别形成在OFF和ON电极的下部的ON和OFF通道区域具有相同的密度。 在形成OFF和ON栅电极之前，形成栅极电介质。
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公开(公告)号：KR100843141B1
公开(公告)日：2008-07-02
申请号：KR1020060045250
申请日：2006-05-19
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/115 , H01L27/11521 , H01L27/11524
Abstract: 비휘발성 메모리 집적 회로 장치가 제공된다. 비휘발성 메모리 집적 횔 장치는 다수의 실질적 직사각형 필드 영역이 매트릭스 형태로 배치되어, 실질적 직사각형 필드 영역의 단변과 장변이 각각 매트릭스의 행방향과 열방향과 평행한 반도체 기판, 반도체 기판 상에 행방향과 평행하도록 연장된 워드 라인과 셀렉트 라인으로, 워드 라인은 매트릭스의 행 방향으로 배치된 다수의 실질적 직사각형 필드 영역 각각과 교차되고, 셀렉트 라인은 매트릭스의 행 방향으로 배치된 다수의 실질적 직사각형 필드 영역 각각과 일부 오버랩되어, 셀렉트 라인의 하부에는 오버랩되는 다수의 실질적 직사각형 필드 영역의 장변의 일부와 단변이 위치하는 워드 라인과 셀렉트 라인, 및 워드 라인과 셀렉트 라인 사이의 반도체 기판 내에 형성된 플로팅 정션 영역과, 워드 라인에 대하여 플로팅 정션 영역의 반대편에 형성된 비트 라인 정션 영역과, 셀렉트 라인에 대하여 플로팅 정션 영역의 반대편에 형성된 커먼 소오스 영역을 포함한다.
셀렉트 게이트, 온셀 전류, 필드 영역
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