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公开(公告)号：KR100852096B1
公开(公告)日：2008-08-13
申请号：KR1020070068313
申请日：2007-07-06
Applicant: 전자부품연구원
IPC: C08F232/00 , C08L77/00
CPC classification number: H05K1/0353 , C08F222/40 , C08G73/126 , C08L79/085 , H05K2201/0158 , Y10T428/31721
Abstract: A thermosetting composite resin composition, a prepreg prepared by using the composition, and a composite film prepared by using the composition are provided to reduce dielectric loss and to allow desired dielectric constant to be obtained. A thermosetting composite resin composition comprises a base resin comprising a cycloolefin polymer of solid state; an organic solvent which dissolves the base resin; a crosslinking agent; an initiator; and at least one inorganic filler selected from BaTiO3, SrTiO3, TiO2, PZT, Al, Cu, Ni, Fe, Ag, Ti, Cr, Si, Mg, Zn, Sn, Pb, Ti, Zr, Ta, Pt, carbon black and graphite, wherein the ratio of the base resin and the crosslinking agent is 95:5 to 80:20 by weight. The composition has a dielectric constant of 4-1,750 according to the content of the inorganic filler.
Abstract translation: 提供一种热固性复合树脂组合物，通过使用该组合物制备的预浸料和通过使用该组合物制备的复合膜，以减少介电损耗并获得所需的介电常数。 热固性复合树脂组合物包含含有固态环烯烃聚合物的基础树脂; 溶解基础树脂的有机溶剂; 交联剂; 发起者 以及选自BaTiO 3，SrTiO 3，TiO 2，PZT，Al，Cu，Ni，Fe，Ag，Ti，Cr，Si，Mg，Zn，Sn，Pb，Ti，Zr，Ta，Pt，炭黑中的至少一种无机填料 和石墨，其中基础树脂和交联剂的比例为95:5至80:20（重量比）。 根据无机填料的含量，该组合物的介电常数为4-1,750。
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公开(公告)号：KR100823998B1
公开(公告)日：2008-04-23
申请号：KR1020070051551
申请日：2007-05-28
Applicant: 전자부품연구원
CPC classification number: B32B15/08 , B32B15/20 , B32B2457/08 , C08J5/24 , H05K1/03
Abstract: A CCL(Copper Clad Laminate), a PCB(Printed Circuit Board), and a CCL manufacturing method are provided to secure high heat resistance and high junction property with copper clad and to increase the dielectric property to the desirable level. A CCL is composed of a prepreg(10) formed by impregnating a low-loss polymer composition with glass fiber and a complex film(20) containing an inorganic filler selected from ceramic and metal materials, carbon black, and graphite and a low-loss polymer composition. The low-loss polymer composition contains thermoplastic resin selected from PPO(Polyphenylene Oxide), copolymer of PPO and PS(Polystyrene), cyclic olefin, and PEI(Polyetherimide) and thermosetting materials applying cross-linking property to the thermoplastic resin. The prepregs are laminated on both ends of a complex film layer formed by laminating the complex films in at least two layers. The copper clad is formed at both ends of the laminated prepreg.
Abstract translation: 提供CCL（铜包层压板），PCB（印刷电路板）和CCL制造方法以确保具有铜包层的高耐热性和高结合性，并将介电性能提高到所需的水平。 CCL由通过用玻璃纤维浸渍低损失聚合物组合物形成的预浸料（10）和含有选自陶瓷和金属材料，炭黑和石墨的无机填料的复合膜（20）和低损耗 聚合物组成。 低损失聚合物组合物含有选自PPO（聚苯醚氧化物），PPO和PS（聚苯乙烯）的共聚物，环烯烃和PEI（聚醚酰亚胺）的热塑性树脂和对热塑性树脂具有交联性的热固性材料。 将预浸料层压在通过将复合膜层压成至少两层形成的复合膜层的两端。 在层压预浸料的两端形成铜包层。
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公开(公告)号：KR1020150111423A
公开(公告)日：2015-10-06
申请号：KR1020140033489
申请日：2014-03-21
Applicant: 전자부품연구원
IPC: H01L21/31 , H01L21/60 , H01L21/304
CPC classification number: H01L21/76877 , H01L21/76843 , H01L21/7685
Abstract: 본발명은반도체소자및 이를제조하는방법에관한것으로써, 보다구체적으로는라미네이션기술을적용한두꺼운절연층을포함한반도체소자및 이를제조하는방법에관한것이다. 본발명은씨모스전력증폭기(CMOS power amplifier), 저잡음증폭기(LNA, Low Noise Amplifier), 전압조정발진기(VCO, voltage controlled oscillator) 등의회로를위한인덕터혹은전송선로와같은수동소자의성능을향상시키는효과가있다.
Abstract translation: 半导体器件及其制造方法技术领域本发明涉及半导体器件及其制造方法，更具体地，涉及使用层叠技术的具有厚绝缘层的半导体器件及其制造方法。 根据本发明，提供了用于CMOS功率放大器，低噪声放大器（LNA），电压控制器振荡器（VCO）的电路等的无源元件的电感器或传输线的性能的提高的效果。 ，等等。
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公开(公告)号：KR101364088B1
公开(公告)日：2014-02-20
申请号：KR1020120101034
申请日：2012-09-12
Applicant: 전자부품연구원
CPC classification number: H01L24/82 , H01L2224/12105 , H01L2224/24 , H01L2224/24137 , H01L2224/24147 , H01L2224/32145 , H01L2224/73267 , H01L2224/92244 , H01L2224/94 , H01L2224/97 , H01L2924/15153 , H01L2924/15311 , H01L2924/15788 , H01L2224/83 , H01L2224/82 , H01L2924/00 , H01L2924/00012
Abstract: A method for manufacturing an interposer includes a step of forming one or more through-vias on a semiconductor substrate; a step of electrically connecting one or more through-vias to a thin-film circuit formed on one side of the semiconductor substrate; and a step of electrically connecting one or more through-vias to an integrated circuit chip formed on the other side of the semiconductor substrate.
Abstract translation: 一种用于制造插入件的方法包括在半导体衬底上形成一个或多个通孔的步骤; 将一个或多个贯通孔电连接到形成在半导体衬底的一侧上的薄膜电路的步骤; 以及将一个或多个贯通孔电连接到形成在半导体基板的另一侧上的集成电路芯片的步骤。
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Patent Agency Ranking
公开(公告)号：KR1020130075552A
公开(公告)日：2013-07-05
申请号：KR1020110143951
申请日：2011-12-27
Applicant: 전자부품연구원
CPC classification number: H01L24/73 , H01L2224/24 , H01L2224/24227 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2224/92244 , H01L2225/1023 , H01L2225/1058 , H01L2924/15153 , H01L2924/15311 , H01L2924/15331 , H01L2924/157 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19105 , H01L2924/19107 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
Abstract: PURPOSE: A semiconductor package and a manufacturing method thereof are provided to implement a thin film type semiconductor package by embedding a thin film passive device in a substrate. CONSTITUTION: At least one first hole is formed on a silicon substrate (110) integrated with a thin film passive device (120). An integrated circuit (130) is inserted into the first hole. A connection member (140) for connecting the integrated circuit to the thin film passive device is formed. An organic insulation layer is made of organic materials by a lamination process. An connection electrode is formed after the connection member is molded. [Reference numerals] (AA,CC) Thin film capacitor; (BB,DD) Spiral inductor
Abstract translation: 目的：提供半导体封装及其制造方法，通过将薄膜无源器件嵌入衬底中来实现薄膜型半导体封装。 构成：在与薄膜无源器件（120）集成的硅衬底（110）上形成至少一个第一孔。 集成电路（130）插入到第一孔中。 形成用于将集成电路连接到薄膜无源器件的连接构件（140）。 有机绝缘层通过层压工艺由有机材料制成。 在连接构件成型后形成连接电极。 （附图标记）（AA，CC）薄膜电容器; （BB，DD）螺旋电感
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公开(公告)号：KR101243304B1
公开(公告)日：2013-03-13
申请号：KR1020110072137
申请日：2011-07-20
Applicant: 전자부품연구원
CPC classification number: H01L2224/04105 , H01L2224/16225 , H01L2224/24 , H01L2224/24195 , H01L2924/15311 , H01L2924/19105 , H01L2924/00012
Abstract: 다층 배선 구조의 인터포저 제조 방법은, 박막 수동 소자가 집적된 실리콘 웨이퍼에 양면 라미네이션 공정을 수행하여 유기 물질의 절연층을 각각 형성한 후에 실리콘을 관통하여 형성되는 공간에 집적 회로를 실장하고 실리콘을 관통하여 형성되는 비아 구멍의 내벽으로 패터닝과 전기 도금을 이용하여 박막 수동 소자의 연결 전극으로 사용되는 라이닝 비아를 형성한다. 다음, 라이닝 비아가 형성된 실리콘 웨이퍼에 양면 라미네이션 공정을 수행하여 유기 물질의 절연층을 각각 형성한 후에 집적 회로의 연결 전극으로 사용되는 라이닝 비아를 형성한다.
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公开(公告)号：KR1020130011171A
公开(公告)日：2013-01-30
申请号：KR1020110072137
申请日：2011-07-20
Applicant: 전자부품연구원
CPC classification number: H01L2224/04105 , H01L2224/16225 , H01L2224/24 , H01L2224/24195 , H01L2924/15311 , H01L2924/19105 , H01L2924/00012
Abstract: PURPOSE: An interposer and a manufacturing method thereof are provided to form a through silicon via with a low loss by forming a thick insulation layer using a lamination process. CONSTITUTION: An interposer(10) is formed with a multilayer interconnection structure and includes a silicon wafer(100), an integrated circuit(110), and a thin film passive device(120). A lining via(130) is formed on a silicon wafer. A lining via(140) is formed on an organic insulation layer of the silicon wafer. A lining via(150) is formed with a coaxial structure.
Abstract translation: 目的：通过使用层压工艺形成厚的绝缘层，提供插入件及其制造方法以形成具有低损耗的硅通孔。 构成：内插器（10）形成有多层互连结构，并且包括硅晶片（100），集成电路（110）和薄膜无源器件（120）。 衬底通孔（130）形成在硅晶片上。 衬底通孔（140）形成在硅晶片的有机绝缘层上。 衬套通孔（150）形成有同轴结构。
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公开(公告)号：KR101115526B1
公开(公告)日：2012-02-27
申请号：KR1020100006617
申请日：2010-01-25
Applicant: 전자부품연구원
IPC: H01L21/60
Abstract: 본 발명은 관통 실리콘 비아(Through Silicon Via; TSV) 제조 방법에 관한 것으로, 특히 폴리머 진공 열압착 공정을 이용한 관통 실리콘 비아 제조 방법에 관한 것이다.
본 발명의 관통 실리콘 비아 제조 방법은 실리콘 기판의 전면에 구멍을 뚫는 (a) 단계; 상기 실리콘 기판의 전면에 폴리머 필름을 놓는 (b) 단계; 진공 상태에서 열과 압력을 이용하여 상기 폴리머 필름을 상기 실리콘 기판의 전면에 접합시키고 상기 구멍에 채워 넣는 (c) 단계; 상기 폴리머 필름으로 메워진 구멍을 처음 뚫을 때의 지름보다 작게 재차 뚫는 (d) 단계; 및 상기 재차 뚫린 구멍을 금속으로 메우는 (e) 단계를 포함하여 이루어진다.
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