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公开(公告)号：KR1019940000155B1
公开(公告)日：1994-01-07
申请号：KR1019900021811
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: H01L21/31
Abstract: The method is characterized by forming a sulfur insulating film on the surface of a compound semiconductor by using a mixed solution of a conventional etching solution and a sulfur treatment solution. In the above method, etching and sulfur treatment can be performed simultaneously by dipping a compound semiconductor into the mixed solution of etching solution of NH4OH + H2O2 + H2O (20:7:973) and sulfur treatment solution of (NH4)2Sx(x=0.2-2.0) at the ratio of 1/0.1-1/10 for 1-10 mins at the initial stage of treating process and a mixed solution of NH4OH + H2O2 + H2O (4:1:4000) and (NH4)2Sx(x=0.2-2.0) at the ratio of 1/0.1-1/10 can be used at the gate recess process.
Abstract translation: 该方法的特征在于通过使用常规蚀刻溶液和硫处理溶液的混合溶液在化合物半导体的表面上形成硫绝缘膜。 在上述方法中，可以通过将化合物半导体浸入NH 4 OH + H 2 O 2 + H 2 O（20:7:973）的蚀刻溶液和（NH 4）2 S x的硫处理溶液（x = 0.2-2.0）在处理初始阶段为1 / 0.1-1 / 10的比例为1-10分钟，NH 4 OH + H 2 O 2 + H 2 O（4:1:4000）和（NH4）2Sx（ x = 0.2-2.0）可以在栅极凹陷处理中使用1 / 0.1-1 / 10的比例。
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公开(公告)号：KR1019930002319B1
公开(公告)日：1993-03-29
申请号：KR1019890012067
申请日：1989-08-24
Applicant: 한국전자통신연구원
Abstract: The transistor is mfd. by forming a non-doped Ga-As layer (2) on the semi-insulating substrate (1), forming a non-doped Al-Ga-As layer (3) on the layer (2), forming a silicon impurity-doped Al-Ga-As source layer (4) on the layer (3), forming a non-doped semi- insulating Al-Ga-As layer (5) on the layer (4), forming a silicon impurity-doped Ga-As layer (6) on layer (5), and partially etching the layer (6) to form a short key contact gate (7) on the layer (5) and to form a resistible contact source (8) and drain (9) on the layer (6).
Abstract translation: 晶体管是mfd。 通过在半绝缘性基板（1）上形成非掺杂Ga-As层（2），在层（2）上形成非掺杂Al-Ga-As层（3），形成杂质掺杂硅 在层（3）上形成Al-Ga-As源层（4），在层（4）上形成非掺杂半绝缘Al-Ga-As层（5），形成掺杂硅杂质的Ga-As 在层（5）上的层（6），并且部分地蚀刻层（6）以在层（5）上形成短键接触栅极（7），并且形成可接触的接触源（8）和漏极（9） 层（6）。
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Patent Agency Ranking
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公开(公告)号：KR1019940004260B1
公开(公告)日：1994-05-19
申请号：KR1019900021807
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: H01L21/335
Abstract: forming a n+-GaAs epitaxial layer 2, n+-GaAs sub-collector layer 3, n-GaAs collector layer 3, p+-base layer 4, n-AlGaAs emitter layer 5 and n+-GaAs cap layer 6 on a GaAs substrate 1 sequentially; forming a photoresist pattern 7 on the n+-GaAs cap layer 6; forming a collector contact region 2a by etching to the n+-GaAs sub-collector layer 3 using the photoresist pattern as a mask; forming a photoresist pattern 7a on the n+-GaAs cap layer 6, and forming a base contact region 4a and emitter contact region 6a by etching the GaAs cap layer 6 and AlGaAs emitter layer 5, and removing the photoresist pattern 7a; forming a AlAs passivation layer 8 and GaAs layer 9 on the collector contact region 2a, base contact region 4a and emitter contact region 6a at the normal temperature sequentially; selective etching the GaAs layer 9 and passivation layer 9; and forming a metal electrodes on the etched portion, thereby reducing the leakage current at the surface of the device.
Abstract translation: 在GaAs衬底1上依次形成n + -GaAs外延层2，n + -GaAs副集电极层3，n-GaAs集电极层3，p + - 基底层4，n-AlGaAs发射极层5和n + -GaAs覆盖层6 ; 在n + -GaAs覆盖层6上形成光刻胶图形7; 通过使用光致抗蚀剂图案作为掩模对n + -GaAs副集电极层3进行蚀刻来形成集电极接触区域2a; 在n + -GaAs覆盖层6上形成光致抗蚀剂图案7a，通过蚀刻GaAs覆盖层6和AlGaAs发射极层5形成基极接触区域4a和发射极接触区域6a，并除去光致抗蚀剂图案7a; 在常温下依次在集电极接触区域2a，基极接触区域4a和发射极接触区域6a上形成AlAs钝化层8和GaAs层9; 选择性蚀刻GaAs层9和钝化层9; 并在蚀刻部分上形成金属电极，从而减少器件表面的漏电流。
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公开(公告)号：KR1019930009551B1
公开(公告)日：1993-10-06
申请号：KR1019900021808
申请日：1990-12-26
Applicant: 한국전자통신연구원
IPC: H01L21/30
Abstract: A passivation layer of hetero-barrier transistor for reducing surface leak current of a semiconductor device, is prepared by (1) forming a sulfur passivation layer with ammonium sulfide ?(NH4)2Sx(x=0.2-2.0)? on the barrier transistor, (2) forming a aluminum arsenide layer(9) and an insulation gallium arsenide layer(10) on the passivation layer by MBE (molecular beam epitaxy) under room temperature and low temperature. It is also used for passivation layer of MESFET, HEMF and laser diode.
Abstract translation: 用于减少半导体器件的表面漏电流的异质阻挡晶体管的钝化层是通过以下步骤制备的：（1）用硫化铵β（NH4）2Sx（x = 0.2-2.0） 在阻挡晶体管上，（2）在室温和低温下通过MBE（分子束外延）在钝化层上形成砷化铝层（9）和绝缘砷化镓层（10）。 它也用于MESFET，HEMF和激光二极管的钝化层。
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