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    이종구조 갈륨 비소 반도체 장치의 소자분리 방법
    7.
    发明授权
    이종구조 갈륨 비소 반도체 장치의 소자분리 방법 失效
    多层GaAs器件的制造方法

    公开(公告)号：KR1019940004274B1

    公开(公告)日：1994-05-19

    申请号：KR1019900021806

    申请日：1990-12-26

    Applicant: 한국전자통신연구원

    Inventor： 이정희 ,  박성호 ,  이종람 ,  김진섭 ,  박형무

    IPC: H01L29/80

    Abstract: forming a first epitaxial layer 2 on a GaAs substrate 1 using molecular beam epitaxy; forming an insulating layer 3 by sequential deposition of a first AlGaAs 3b, GaAs 3c and a second AlGaAs 3a on first epitaxial layer 2, first AlGaAs layer 3b and second AlGaAs layer 3a are formed at the same temperature, and GaAs layer 3c is formed at the temperature lower than that of AlGaAs layer 3a,3b; forming an second epitaxial layer 4 on the insulating layer 3; selective etching second AlGaAs layer 3a, GaAs layer 3c and first Al GaAs layer 3b so as to expose first epitaxial layer 2 and second epitaxial layer 4a; forming a metal pattern 6 on an active region of each device; forming a predetermined photoresist pattern 5a on the surface of the substrate; forming an isolation region 7 in the vertical derection to the substrate by ion implanting into the substrate using the photoresist pattern 5a as mask, thereby to shut off the current between the the devices without damaging to the substrate.

    Abstract translation: 使用分子束外延在GaAs衬底1上形成第一外延层2; 通过在第一外延层2上顺序沉积第一AlGaAs 3b，GaAs 3c和第二AlGaAs 3a来形成绝缘层3，在相同温度下形成第一AlGaAs层3b和第二AlGaAs层3a，并且形成GaAs层3c 温度低于AlGaAs层3a，3b; 在绝缘层3上形成第二外延层4; 选择性蚀刻第二AlGaAs层3a，GaAs层3c和第一Al GaAs层3b，以暴露第一外延层2和第二外延层4a; 在每个装置的有源区上形成金属图案6; 在所述基板的表面上形成预定的光致抗蚀剂图案5a; 通过使用光致抗蚀剂图案5a作为掩模将衬底中的离子注入到衬底中，在垂直于衬底的垂直方向上形成隔离区域7，从而切断器件之间的电流而不损坏衬底。

    금속절연체 전계효과 트랜지스터의 제조방법
    8.
    发明授权
    금속절연체 전계효과 트랜지스터의 제조방법 失效
    通过加工硫磺制备MISFET的制备方法

    公开(公告)号：KR1019940004261B1

    公开(公告)日：1994-05-19

    申请号：KR1019900021810

    申请日：1990-12-26

    Applicant: 한국전자통신연구원

    Inventor： 이종람 ,  박성호 ,  박철순 ,  김진섭 ,  박형무

    IPC: H01L21/335

    Abstract: forming a carrier channel layer 2 on a GaAs substrate 1; forming a passivation layer 3 and a GaAs semiconductor layer 4 on the overall surface of the carrier channel layer, and forming a substrate pattern with mesa shape; forming a insulating layer 5 on the GaAs layer 4; forming a gate insulating layer 5a by etching the insulating layer 5 and GaAs layer 4; forming a gate on the gate insulating layer 5a; forming a source region and drain region by selective implantation of silicon ion into the passivation layer 3; and forming a source 8 and drain 9 on the source region and drain region, thereby improving the operating speed and high frequency characteristics of the metal-insulator field effect transistor.

    Abstract translation: 在GaAs衬底1上形成载流子通道层2; 在载流子通道层的整个表面上形成钝化层3和GaAs半导体层4，并形成台面形状的衬底图形; 在GaAs层4上形成绝缘层5; 通过蚀刻绝缘层5和GaAs层4形成栅极绝缘层5a; 在栅极绝缘层5a上形成栅极; 通过将硅离子选择性地注入到钝化层3中来形成源极区和漏极区; 并在源极区域和漏极区域上形成源极8和漏极9，从而提高金属 - 绝缘体场效应晶体管的工作速度和高频特性。

    재 성장법을 이용한 구조가 다른 에피층의 제조방법
    9.
    发明授权
    재 성장법을 이용한 구조가 다른 에피층의 제조방법 失效
    通过再生长方法制造具有不同结构的外延层的方法

    公开(公告)号：KR1019920010132B1

    公开(公告)日：1992-11-16

    申请号：KR1019890012336

    申请日：1989-08-29

    Applicant: 한국전자통신연구원

    Inventor： 이재진 ,  맹성재 ,  김진섭

    IPC: H01L21/36

    CPC classification number: G01N33/64 ,  C12Q1/26 ,  C12Q1/32 ,  C12Q1/34 ,  C12Q1/37 ,  C12Q1/40 ,  C12Q1/48 ,  C12Q1/527 ,  C12Q2334/10 ,  C12Q2337/12 ,  G01N33/84 ,  G01N2333/9121 ,  G01N2333/924 ,  Y10S435/962

    Abstract: The method uses a regrowing process to form epitaxial layers onto a substrate, the epitaxial layers having different structures respectively, thereby mounting multifunctional elements on a single chip. The method comprises the steps of depositing a dielectric layer (13) onto a first epitaxial layer (12) grown on a semiconductor substrate (11), etching the desired portions of the layers (12,13) to form a mesa structure (12a,13a), regrowing second epitaxial layer (14) thereon, and removing the dielectric layer (13a) and the second epilaxial layer (14a) formed on the layer (13a) by using a lift-off process, thereby forming two different epitaxial layers (12a,14) on a substrate (11).

    Abstract translation: 该方法使用再生过程在衬底上形成外延层，外延层分别具有不同的结构，从而将多功能元件安装在单个芯片上。 该方法包括以下步骤：在生长在半导体衬底（11）上的第一外延层（12）上沉积介电层（13），蚀刻所述层（12,13）的所需部分以形成台面结构（12a， 在其上重新生长第二外延层（14），并通过剥离工艺去除形成在层（13a）上的电介质层（13a）和第二外延层（14a），从而形成两个不同的外延层（ 12a，14）。

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