公开(公告)号：KR1020110055023A

公开(公告)日：2011-05-25

申请号：KR1020090111880

申请日：2009-11-19

Applicant: 한국전자통신연구원

Inventor： 민병훈

IPC: H03L7/093 ,  H03L7/08

CPC classification number: H03L7/0893 ,  H03L7/093

Abstract: PURPOSE: A loop filter and a phase locked loop comprising the same are provided to replace a first capacitor having a high value with the capacitor having a low value. CONSTITUTION: A first filter path(331) filters first current applied to a first input node at first, and a second filter path(332) includes a second capacitor connected between a first input node and the ground. A second filter path secondly filters the first current applied to the first input node. A third filter path(333) includes a third capacitor connected between a third resistor and the ground of the output node, wherein the third resistor is connected between the first input node and an output node.

Abstract translation: 目的：提供一种环路滤波器和包括该环路滤波器的锁相环，以替代具有低值的电容器具有高值的第一电容器。 构成：第一滤波器路径（331）首先对施加到第一输入节点的第一电流进行滤波，并且第二滤波器路径（332）包括连接在第一输入节点和地之间的第二电容器。 第二滤波器路径二次过滤施加到第一输入节点的第一电流。 第三滤波器路径（333）包括连接在第三电阻器和输出节点的地之间的第三电容器，其中第三电阻器连接在第一输入节点和输出节点之间。

公开(公告)号：KR1020100063636A

公开(公告)日：2010-06-11

申请号：KR1020090055584

申请日：2009-06-22

Applicant: 한국전자통신연구원

Inventor： 이자열 ,  민병훈 ,  김성도 ,  유현규

IPC: H03B5/08 ,  H03L7/099

CPC classification number: H01L28/40 ,  H03B5/1228 ,  H03B5/1243 ,  H03B2201/0208 ,  H03L7/099

Abstract: PURPOSE: A capacitor with variable capacitance and a digital control oscillator thereof are provided to reduce power consumption or the area of a chip by reducing the use of a digital circuit block which is used for improving the frequency resolution of a digital phase locked loop frequency synthesizer. CONSTITUTION: A lamination structure(10) comprises a plurality of metal layers including a first metal layer(111) and a plurality of dielectric layers(121,122) which are inserted between a plurality of metal layers. A switching unit, which has at least one switch, is connected to at least one metal layer among the metal layers excluding the first metal layer. The first metal layer and one end of the switch are used as a positive terminal of the capacitor. Two or more capacitances are provided through the short-circuit and open control of the switch.

Abstract translation: 目的：提供具有可变电容的电容器及其数字控制振荡器，以通过减少用于提高数字锁相环频率合成器的频率分辨率的数字电路块的使用来降低功耗或芯片面积 。 构成：层叠结构（10）包括多个金属层，包括插入在多个金属层之间的第一金属层（111）和多个电介质层（121,122）。 具有至少一个开关的切换单元连接到除了第一金属层之外的金属层中的至少一个金属层。 第一金属层和开关的一端用作电容器的正极。 通过开关的短路和开路控制提供两个或多个电容。

公开(公告)号：KR1020100062806A

公开(公告)日：2010-06-10

申请号：KR1020090023897

申请日：2009-03-20

Applicant: 한국전자통신연구원

Inventor： 민병훈 ,  이자열 ,  김성도 ,  김천수 ,  유현규

IPC: H03L7/16 ,  H03L7/00

CPC classification number: H03L7/1075 ,  H03L7/085 ,  H03L7/093 ,  H03L7/1976

Abstract: PURPOSE: A frequency adjustment loop is provided to form a lock state of the frequency adjustment loop within fast time by moving an output frequency of an oscillator to wanting frequency band. CONSTITUTION: An oscillator(140) controls an output frequency according to inputted control bit. A programmable divider(150) divides the output frequency of the oscillator according to varied dividing ratio. A counter unit(110) is inputted an output signal of the programmable divider and a reference frequency. The counter unit measures a clock number of the output signal of the divider in one period of the reference frequency. A frequency detector(120) outputs the value tacking out from the clock number outputted from the counter unit in a standard comparison value to a control bit of the oscillator. The programmable divider decides the divide ratio about the output signal of the oscillator by receiving a feedback the clock number outputted from the counter unit.

Abstract translation: 目的：通过将振荡器的输出频率移动到想要的频带，提供频率调整回路以在快速时间内形成频率调节回路的锁定状态。 构成：振荡器（140）根据输入的控制位控制输出频率。 可编程分频器（150）根据分频比分频振荡器的输出频率。 计数器单元（110）输入可编程分频器的输出信号和参考频率。 计数器单元在参考频率的一个周期内测量分频器的输出信号的时钟数。 频率检测器（120）将从标准比较值中的从计数器单元输出的时钟编号输出的值输出到振荡器的控制位。 可编程分频器通过从计数器单元输出的时钟数字接收反馈来决定关于振荡器输出信号的分频比。

公开(公告)号：KR1020090035362A

公开(公告)日：2009-04-09

申请号：KR1020070100608

申请日：2007-10-05

Applicant: 한국전자통신연구원

Inventor： 민병훈 ,  김영호 ,  박경환 ,  현석봉

IPC: H01L29/93

CPC classification number: H01L29/93 ,  H01L27/0808

Abstract: A differential varactor is provided to improve common mode rejection ratio by forming gate varactor as a differential varactor. A first input terminal is connected with a source electrode of a first and a third gate varactor through a first and a third capacitor. A second input terminal a source of the second and fourth varactor through a second and fourth capacitor commonly. A source electrode of the first and the second gate varactor supplies positive bias voltage through a third and a fourth resistor(R3,R4). A source electrode of the third and fourth gate varactor supplies negative voltage through a fifth and a sixth resistor.

Abstract translation: 提供差分变容二极管，通过将门变容二极管形成为差分变容二极管来提高共模抑制比。 第一输入端子通过第一和第三电容器与第一和第三栅极变容二极管的源极连接。 通过第二和第四电容器，第二输入端子是第二和第四变容二极管的源极。 第一和第二栅极变容二极管的源电极通过第三和第四电阻器（R3，R4）提供正偏置电压。 第三和第四栅极变容二极管的源电极通过第五和第六电阻器提供负电压。