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公开(公告)号：KR1019920003286B1
公开(公告)日：1992-04-27
申请号：KR1019890019673
申请日：1989-12-27
Applicant: 한국전자통신연구원
IPC: G06F13/38
Abstract: Synchronizing clock pulses are generated by a central slot (12) so as to be supplied through signal lines of a back plane (11). Two outer slots (13)(14) and (15)(16) which are adjacent to each other, and which are located outwardly from the central slot (12) are electrically bundled together as groups. The lengths of the signal lines of the back plane (11), which connect the groups to the central slot (12), are made to be the same, so that bus clocks of the central slot (12) should reach the groups simultaneously. The method simplifys the circuit constitution, to facilitate a serial termination, and minimizes the load of the signal receiving end.
Abstract translation: 同步时钟脉冲由中心槽（12）产生，以便通过背板（11）的信号线提供。 彼此相邻并从中心狭槽（12）向外定位的两个外槽（13）（14）和（15）（16）被组合在一起。 将组合到中心狭槽（12）的背板（11）的信号线的长度相同，使得中心槽（12）的总线时钟同时到达组。 该方法简化了电路结构，便于串行终端，并使信号接收端的负载最小化。
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Patent Agency Ranking
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公开(公告)号：KR1019920000480B1
公开(公告)日：1992-01-14
申请号：KR1019890019308
申请日：1989-12-22
Applicant: 한국전자통신연구원
IPC: G06F13/32
Abstract: The method is to support interprocess communication of multiprocessor system. When an interrupt request signal is received, arbiters are drived fromthe first bit according to thepriorities to allow the usage of interrupt bus for processors. The circuit includes an interrupt requester (5) for request arbitration to interrupt handlers (3,4) when the interrupt request signal from processors (1,2) is received, interrupt handlers (3,4) for processing the arbitration request and interrupts occured in boards in which processors are deposited, an interrupt arbiter (7) for executing the arbitration and sending the result to the interrupt requestor (5), and for arbitrating the interrupt handlers, and an interrupt bus synchronizing signal (IBSYNC) driver (8) for generating the IBSYNC signal to drive the signal line (9) and for sending the IBSYNC signal to the interrupt requester (5).
Abstract translation: 该方法是支持多处理器系统的进程间通信。 当接收到中断请求信号时，根据优先级从第一位驱动仲裁器，以允许对处理器使用中断总线。 当接收到来自处理器（1,2）的中断请求信号时，该电路包括用于请求仲裁以中断处理程序（3,4）的中断请求器（5），用于处理仲裁请求的中断处理程序（3,4） 在处理器存放的板中，执行仲裁并将结果发送给中断请求者（5）并用于仲裁中断处理程序的中断仲裁器（7）和中断总线同步信号（IBSYNC）驱动器（8） 用于产生IBSYNC信号以驱动信号线（9）并将IBSYNC信号发送到中断请求器（5）。
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公开(公告)号：KR1019940006833B1
公开(公告)日：1994-07-28
申请号：KR1019910019572
申请日：1991-11-05
Applicant: 한국전자통신연구원
IPC: G06F15/16
Abstract: The apparatus improves the performance of the overall system so that the desired data can be accessed no matter what the system bus size is. The system comprises; a shared resource memory unit (22); an address buffer storing the specified area address of the shared resource; a control and decoder unit (24) controlling a bidirectional buffer (21) and the shared memory unit (22) in order to transmit the stored data of the memory unit into the bidirectional buffer; a buffer (23) summing the address from the decoder (24) and the address from an address buffer (25).
Abstract translation: 该装置改善了整个系统的性能，使得无论系统总线大小是什么，都可以访问所需的数据。 该系统包括 共享资源存储单元（22）; 存储共享资源的指定区域地址的地址缓冲器; 控制和解码器单元（24），用于控制双向缓冲器（21）和共享存储器单元（22），以便将存储单元的存储数据传输到双向缓冲器中; 缓冲器（23）将来自解码器（24）的地址和来自地址缓冲器（25）的地址相加。
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