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公开(公告)号：KR1019900003751B1
公开(公告)日：1990-05-31
申请号：KR1019870006241
申请日：1987-06-19
Applicant: 한국전자통신연구원
IPC: G06F13/20
Abstract: A microprocessor, RAM, ROM, trigger control logic (TCL), a trace control logic (TRCL), trace memory (TR-M), terminal interface logic (TIL) are connected through a local bus in one board. The TRCL, TR-M, and TIL are connected to a backplane bus thrugh a bus interface logic (BIL) and the TIL is connected to a general terminal (G-TM). When the user enters the command for information search or storage through the terminal, the microprocessor compares the backplane bus information coming through the BIL with the trigger condition of the TCL and the TRCL stores the information into the TR-M during the preset bus cycle if the conditions are matched with each other.
Abstract translation: 微处理器，RAM，ROM，触发控制逻辑（TCL），跟踪控制逻辑（TRCL），跟踪存储器（TR-M），终端接口逻辑（TIL）通过一个板上的本地总线连接。 TRCL，TR-M和TIL通过总线接口逻辑（BIL）连接到背板总线，TIL连接到通用终端（G-TM）。 当用户通过终端输入信息搜索或存储命令时，微处理器将通过BIL的背板总线信息与TCL的触发条件进行比较，TRCL在预置的总线周期内将信息存储到TR-M中，如果 条件相互匹配。
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公开(公告)号：KR1019920007170B1
公开(公告)日：1992-08-27
申请号：KR1019890019307
申请日：1989-12-22
Applicant: 한국전자통신연구원
IPC: G06F13/32
Abstract: The interrupt bus is for communicating asynchronous signals between modules of multiprocessor system. The unit includes an inerrupt requester (4) for sending interrupt transmission request signal of system module to a corresponding interrupt processor, interrupt processors (5,6) for sending interrupt signal to the corresponding module, an interrupt signal to the corresponding module, an interrupt arbiter (7) for arbitrating the usage of the interrupt bus, a first and a second interrupt requester register (8,10) for storing data of the interrupt requester, a first and a second interrupt processor register, and adaptors (12,13) for forming signal line among the interrupt requestor (4), the interrup processors (5,6) and the interrupt bus (3).
Abstract translation: 中断总线用于在多处理器系统的模块之间传送异步信号。 该单元包括用于向对应的中断处理器发送系统模块的中断发送请求信号的中断请求器（4），用于向相应模块发送中断信号的中断处理器（5,6），对应模块的中断信号，中断 用于仲裁中断总线的使用的仲裁器（7），用于存储中断请求者的数据的第一和第二中断请求者寄存器（8,10），第一和第二中断处理器寄存器以及适配器（12,13） 用于在中断请求器（4），中断处理器（5,6）和中断总线（3）之间形成信号线。
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Patent Agency Ranking
公开(公告)号：KR1019920003285B1
公开(公告)日：1992-04-27
申请号：KR1019890019305
申请日：1989-12-22
Applicant: 한국전자통신연구원
IPC: G06F13/00
Abstract: transmissions of ordinary reading and writing, reading for reading, reading for writing, write-back and invalid cash identity and transmissions of interlock reading, and interlock writing for processor-read data corrections. The transmissions are carried out through a requestor (10) and a responder (20). The method transmits data by breaking down into above mentioned forms, so that the translating section of the receiving end recognizes the cause of the data source and its purpose.
Abstract translation: 普通阅读和写作的读取，阅读阅读，写作阅读，回写和无效现金身份以及联锁读取的传输，以及用于处理器读取数据更正的联锁写入。 传输通过请求者（10）和响应者（20）进行。 该方法通过分解成上述形式发送数据，使得接收端的翻译部分识别数据源的原因及其目的。
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公开(公告)号：KR1019920000479B1
公开(公告)日：1992-01-14
申请号：KR1019890019311
申请日：1989-12-22
Applicant: 한국전자통신연구원
IPC: G06F13/00
Abstract: The read modify write (RMW) is executed not occupying system bus for synchronizing the processors of multi process system. The method includes the steps: (A) checking RMW transmission type in a data transmission type generator and a data transmission bus requester (3); (B) discriminating the write or read operation of RMW; (C) executing interlock read operation and receiving AACK signal at RMW read operation; otherwise (D) executing interlock write operation, and checking the locking state using a locking transmission type processor and data transmission bus interfacer (5); (E) sending lock busy signal and OK signal to the bus requester when the bus is locked by the interlock read; and (F) when the bus is locked by the interlock write, sending OK signal, releasing the lock, writing data and sending error signal at the same time.
Abstract translation: 执行读修改写（RMW）不占用用于同步多进程系统的处理器的系统总线。 该方法包括以下步骤：（A）检查数据传输类型发生器和数据传输总线请求器（3）中的RMW传输类型; （B）识别RMW的写入或读取操作; （C）执行联锁读操作，并以RMW读操作接收AACK信号; 否则（D）执行联锁写入操作，并使用锁定传输类型处理器和数据传输总线接口（5）检查锁定状态; （E）当总线被互锁读取锁定时，向总线请求者发送锁定忙信号和OK信号; 和（F）当总线通过互锁写入锁定时，发送OK信号，释放锁定，同时写入数据和发送错误信号。
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