公开(公告)号：WO1998004892A1

公开(公告)日：1998-02-05

申请号：PCT/US1997005113

申请日：1997-03-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  DAWSON, Robert ,  HAUSE, Frederick, N. ,  MAY, Charles, E.

IPC: G01J05/60

CPC classification number: G01J5/601 ,  G01J5/041 ,  G01J5/60

Abstract: A broadband pyrometer is used for sensing temperature of a semiconductor wafer in an RTA system in association with a monochromator to cancel the backside characteristics of the semiconductor wafer. A rapid thermal anneal (RTA) system includes a rapid thermal anneal (RTA) chamber, a heating lamp arranged in the vicinity of the RTA chamber for heating interior to the RTA chamber, a broadband pyrometer disposed in the vicinity of the RTA chamber and directed to measure interior to the RTA chamber, and a grating monochromator connected to the broadband pyrometer.

Abstract translation: 使用宽带高温计来检测与单色仪相关联的RTA系统中的半导体晶片的温度，以消除半导体晶片的背面特性。 快速热退火（RTA）系统包括快速热退火（RTA）室，布置在RTA室附近的加热灯，用于加热到RTA室内部，宽带高温计设置在RTA室附近并被引导 测量RTA室的内部，以及连接到宽带高温计的光栅单色仪。

公开(公告)号：WO1998003994A1

公开(公告)日：1998-01-29

申请号：PCT/US1997009452

申请日：1997-05-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  BANDYOPADHYAY, Basab ,  FULFORD, H., Jim, Jr. ,  DAWSON, Robert ,  HAUSE, Fred, N. ,  MICHAEL, Mark, W. ,  BRENNAN, William, S.

IPC: H01L21/768

CPC classification number: H01L23/5222 ,  H01L21/76816 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multilevel interconnect structure (10) is provided. The multilevel interconnect structure includes at least three levels of interconnect (conductors) formed according to one exemplary embodiment. Two of the three levels (12) of conductors are staggered from each other (16) in separate vertical and horizontal planes. A third conductor (16) is advantageously spaced a lateral distance between at least a portion of two second conductors (26). The third conductor is also placed in an elevational level below or possibly above the second conductor so as to reduce the capacitive coupling therebetween. By staggering the second and third conductors, high density interconnect can be achieved with minimal propagation delay and cross coupling.

Abstract translation: 提供了多层互连结构（10）。 多层互连结构包括根据一个示例性实施例形成的至少三层互连（导体）。 导体的三个层（12）中的两个在单独的垂直和水平平面中彼此交错（16）。 第三导体（16）有利地在两个第二导体（26）的至少一部分之间隔开横向距离。 第三导体也被放置在第二导体的下方或可能的第二导体的上方，以减小它们之间的电容耦合。 通过交错第二和第三导体，可以以最小的传播延迟和交叉耦合实现高密度互连。

公开(公告)号：WO1998002918A1

公开(公告)日：1998-01-22

申请号：PCT/US1997005176

申请日：1997-03-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GARDNER, Mark, I. ,  DUANE, Michael, P. ,  WRISTERS, Derick, J.

IPC: H01L21/336

CPC classification number: H01L29/66659 ,  H01L29/7835

Abstract: A method for fabrication of a non-symmetrical LDD-IGFET is described. In one embodiment, the method includes providing a semiconductor substrate having a gate insulator (104) and a gate electrode (106), the gate electrode having opposing first and second sidewalls (103, 105) defining the length of the gate electrode and a top surface. Lightly doped source (108) and drain (110) regions are implanted into the semiconductor substrate and are substantially aligned with the sidewalls of the gate electrode. After implanting the lightly doped regions, first and second spacers (112, 114) are formed adjacent to the first and second sidewalls of the gate electrode. After forming the spacers, a portion of the gate electrode is removed to form a third sidewall (117) of the gate electrode opposite the second sidewall (105), thereby eliminating the first sidewall and reducing the length of the gate electrode. After removing the first spacer, heavily doped source (120) and drain (118) regions are implanted into the semiconductor substrate. The heavily doped drain region is substantially aligned with the outer edge of the second spacer, a portion of the lightly doped drain regions is protected beneath the second spacer, and the heavily doped source region is substantially aligned with the third sidewall. In another embodiment, the heavily doped drain region is implanted after the spacers are formed but before the third sidewall is formed and the heavily doped source region is implanted after forming the third sidewall.

Abstract translation: 描述了一种用于制造非对称LDD-IGFET的方法。 在一个实施例中，该方法包括提供具有栅极绝缘体（104）和栅电极（106）的半导体衬底，所述栅电极具有限定栅电极的长度的相对的第一和第二侧壁（103,105） 表面。 将轻掺杂源（108）和漏极（110）区域注入到半导体衬底中并且基本上与栅电极的侧壁对准。 在注入轻掺杂区域之后，第一和第二间隔物（112,114）邻近栅电极的第一和第二侧壁形成。 在形成间隔物之后，去除栅电极的一部分以形成与第二侧壁（105）相对的栅电极的第三侧壁（117），由此消除第一侧壁并减小栅电极的长度。 在去除第一间隔物之后，将重掺杂的源极（120）和漏极（118）区域注入到半导体衬底中。 重掺杂漏极区域基本上与第二间隔物的外边缘对准，轻掺杂漏极区域的一部分被保护在第二间隔物下方，并且重掺杂源极区域基本上与第三侧壁对准。 在另一个实施例中，在形成间隔物之后但在形成第三侧壁之前注入重掺杂漏极区，并且在形成第三侧壁之后注入重掺杂源极区。

公开(公告)号：WO1998002913A2

公开(公告)日：1998-01-22

申请号：PCT/US1997005089

申请日：1997-03-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GARDNER, Mark, I. ,  WRISTERS, Derick, J. ,  FULFORD, H., Jim

IPC: H01L21/033

CPC classification number: G03F7/70466 ,  G03F7/00 ,  H01L21/0337 ,  Y10S438/947

Abstract: A method of forming a gate electrode for an insulated-gatefield-effectransistor (IGFET) is disclosed. The method includes forming a gate material for providing a gate electrode over a semiconductor substrate, forming a first mask over the gate material wherein the first mask includes an opening that defines a first edge of the gate electrode, removing a first portion of the gate material to form the first edge of the gate electrode as defined by the first mask, forming a second mask over the gate material after removing the first mask wherein the second mask includes an opening that defines a second edge of the gate electrode, removing a second portion of the gate material to form the second edge of the gate electrode as defined by the second mask, and removing the second mask. Thus, the gate electrode is defined by a lateral displacement between the openings in the first and second masks. Preferably, the first and second masks are photoresist, and the length between the first and second edges of the gate electrode is less than the minimum resolution of a photolithographic system used to pattern the masks.

Abstract translation: 公开了一种形成绝缘栅场效应晶体管（IGFET）的栅电极的方法。 该方法包括形成用于在半导体衬底上提供栅电极的栅极材料，在栅极材料上形成第一掩模，其中第一掩模包括限定栅电极的第一边缘的开口，去除栅极材料的第一部分 以形成由第一掩模限定的栅电极的第一边缘，在去除第一掩模之后在栅极材料上形成第二掩模，其中第二掩模包括限定栅电极的第二边缘的开口，去除第二部分 以形成由第二掩模限定的栅电极的第二边缘，并且移除第二掩模。 因此，栅电极由第一和第二掩模中的开口之间的横向位移限定。 优选地，第一和第二掩模是光致抗蚀剂，并且栅电极的第一和第二边缘之间的长度小于用于对掩模进行图案化的光刻系统的最小分辨率。

公开(公告)号：WO1998002806A1

公开(公告)日：1998-01-22

申请号：PCT/US1996011847

申请日：1996-07-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  PICKETT, James, K.

IPC: G06F09/38

CPC classification number: G06F9/383 ,  G06F9/3455 ,  G06F9/3832

Abstract: A data prediction structure is provided. The data prediction structure stores base addresses and stride values in a prediction array. The base address and the stride value are added to form a data prediction address which is then used to fetch data bytes into a relatively small, relatively fast buffer which may be accessed by the decode stage(s) of the instruction processing pipeline. If the data associated with an operand address calculated by a decode stage resides in the buffer, the clock cycles used to perform the load operation occur before the instruction reaches the execution stage of the instruction processing pipeline. The execution stage clock cycles that are saved may be used to execute other instructions. Additionally, the base address is updated to the address generated by a decode unit each time a basic block is executed, and the stride value is updated when the data prediction address is found to be incorrect. In this way, the data prediction address may be more accurate than a static data prediction address.

Abstract translation: 提供了一种数据预测结构。 数据预测结构将基地址和步幅值存储在预测数组中。 添加基地址和步幅值以形成数据预测地址，然后将数据预测地址用于将数据字节提取到可由指令处理流水线的解码级访问的较小的相对较快的缓冲器中。 如果与由解码级计算的操作数地址相关联的数据位于缓冲器中，则用于执行加载操作的时钟周期在指令到达指令处理流水线的执行阶段之前发生。 保存的执行阶段时钟周期可用于执行其他指令。 此外，每当执行基本块时，基地址被更新为由解码单元生成的地址，并且当发现数据预测地址不正确时更新步幅值。 以这种方式，数据预测地址可能比静态数据预测地址更准确。

公开(公告)号：WO1998002798A1

公开(公告)日：1998-01-22

申请号：PCT/US1996011759

申请日：1996-07-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  TRAN, Thang, M. ,  WITT, David, B. ,  JOHNSON, William, M.

IPC: G06F09/30

CPC classification number: G06F9/3816 ,  G06F9/30152 ,  G06F9/382 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855

Abstract: A superscalar microprocessor having an instruction alignment unit, an instruction cache, a plurality of decode units and a predecode unit is provided. The instruction alignment unit transfers a fixed number of instructions from the instruction cache to each of the plurality of decode units. The instructions are selected from a quantity of bytes according to a predecode tag generated by the predecode unit. The predecode tag includes start-byte bits that indicate which bytes within the quantity of bytes are the first byte of an instruction. The instruction alignment unit independently scans a plurality of groups of instruction bytes, selecting start bytes and a plurality of contiguous bytes for each of a plurality of issue positions. Initially, the instruction alignment unit selects a group of issue positions for each of the plurality of groups of instructions. The instruction alignment unit then shifts and merges the independently produced issue positions to produce a final set of issue positions for transfer to the plurality of decode units.

Abstract translation: 提供了具有指令对准单元，指令高速缓存，多个解码单元和预解码单元的超标量微处理器。 指令对准单元将固定数量的指令从指令高速缓存传送到多个解码单元中的每一个。 根据由预解码单元生成的预解码标签，从一定量的字节中选择指令。 预解码标签包含开始字节位，指示字节数中的哪个字节是指令的第一个字节。 指令对准单元独立地扫描多组指令字节，为多个发行位置中的每一个选择开始字节和多个连续字节。 最初，指令对准单元为多组指令中的每一组选择一组发行位置。 指令对准单元然后移动并合并独立产生的问题位置，以产生用于传送到多个解码单元的发布位置的最后一组。

公开(公告)号：WO1998000958A1

公开(公告)日：1998-01-08

申请号：PCT/US1997011255

申请日：1997-06-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GUERCIO, David, J. ,  GREENWELL, Paul, E. ,  BORLAND, David, J.

IPC: H04M01/57

CPC classification number: H04M1/57 ,  H04M1/578 ,  H04M3/02 ,  H04M3/42042 ,  H04M3/42059 ,  H04M3/53391 ,  H04M2242/22

Abstract: Presented is a telephone calling party announcement system which stores telephone numbers and associated voice messages provided by a user. When an incoming telephone call occurs, and a telephone number of a calling party matches a stored telephone number, an associated stored voice message is played back. Calling party information is provided by Caller ID information transmitted between a first and a second ring signal. If a stored telephone number matches the telephone number portion of the Caller ID information, a stored voice message associated with the telephone number is played back between (or in place of) subsequent ring signals. The stored voice message is typically the name of the calling party, and in this case the name of the calling party is announced between ring signals. A first embodiment includes a voice message unit which receives, stores, and plays back voice messages provided by the user. A caller ID decoder decodes the Caller ID information and provides the decoded Caller ID information to a control unit. The control unit compares the telephone number portion of the decoded Caller ID information to telephone numbers stored in a control memory unit. If a match is found, the control unit asserts a playback control signal which causes the voice message unit to play back an associated stored voice message. In a second embodiment, a digital signal processor (DSP) performs many of the functions of the voice message unit and the caller ID decoder of the first embodiment.

Abstract translation: 提出了一种电话呼叫方公告系统，其存储由用户提供的电话号码和相关语音消息。 当进入电话呼叫并且主叫方的电话号码与存储的电话号码相匹配时，播放相关联的存储的语音消息。 呼叫方信息由在第一和第二振铃信号之间传送的呼叫者ID信息提供。 如果存储的电话号码与来电显示信息的电话号码部分相匹配，则在（或替代）随后的振铃信号之间播放与电话号码相关联的存储的语音消息。 存储的语音消息通常是呼叫方的名称，在这种情况下，呼叫方的名称在振铃信号之间被公布。 第一实施例包括语音消息单元，其接收，存储和重放由用户提供的语音消息。 呼叫者ID解码器解码来电显示信息，并将解码的来电显示信息提供给控制单元。 控制单元将解码的来电显示信息的电话号码部分与存储在控制存储器单元中的电话号码进行比较。 如果发现匹配，则控制单元断言使语音消息单元播放相关联的存储的语音消息的播放控制信号。 在第二实施例中，数字信号处理器（DSP）执行第一实施例的语音消息单元和呼叫者ID解码器的许多功能。

公开(公告)号：WO1997049089A1

公开(公告)日：1997-12-24

申请号：PCT/US1997005218

申请日：1997-03-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HU, Chung-You ,  SUN, Yu ,  HADDAD, Sameer ,  CHANG, Chi

IPC: G11C16/04

CPC classification number: G11C16/0483

Abstract: The present invention facilitates programming of selected floating gate devices while successfully inhibiting the programming of unselected devices, without the need for growing multiple thicknesses of oxides. The preferred embodiment of the present invention utilizes a multiple select gate device. In particular, the select gate device is preferably a dual floating gate device rather than the conventional transistor (or device functioning as a conventional transistor) used in the current Flash memory systems as a select gate device.

Abstract translation: 本发明有助于编程所选择的浮动栅极器件，同时成功地禁止对未选择器件的编程，而不需要生长多个厚度的氧化物。 本发明的优选实施例利用多选择栅极器件。 特别地，选择栅极器件优选地是双浮置栅极器件，而不是在当前闪存存储器系统中用作选择栅极器件的常规晶体管（或用作常规晶体管的器件）。

公开(公告)号：WO1997047038A1

公开(公告)日：1997-12-11

申请号：PCT/US1997002329

申请日：1997-02-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  DAWSON, Robert ,  MICHAEL, Mark, W. ,  BANDYOPADHYAY, Basab ,  FULFORD, H., Jim, Jr. ,  HAUSE, Fred, N. ,  BRENNAN, William, S.

IPC: H01L23/522

CPC classification number: H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors (14, 16), wherein conductors (14) on one level are staggered with respect to conductors (11) on another level. Accordingly, a space (32, 34) between conductors on one level is directly above or directly below a conductor within another level. The staggered interconnect lines are advantageously used in densely spaced regions to reduce the interlevel and intralevel capacitance. Furthermore, an interlevel and an intralevel dielectric structure includes optimally placed low K dielectrics (24) which exist in critical spaced areas to minimize capacitive coupling and propagation delay problems. The low K dielectric, according to one embodiment, includes a capping dielectric which is used to prevent corrosion on adjacent metallic conductors, and serves as an etch stop when conductors are patterned. The capping dielectric further minimizes the overal intrinsic stress of the resulting intralevel and interlevel dielectric structure.

Abstract translation: 提供了一种改进的多级互连结构。 互连结构包括几层导体（14,16），其中一个层上的导体（14）相对于另一层上的导体（11）交错。 因此，一个级别的导体之间的空间（32,34）直接在另一个水平的导体的正上方或正下方。 交错的互连线有利地用于密集间隔的区域以减少层间和层间电容。 此外，层间和层间介质结构包括存在于临界间隔区域中的最佳放置的低K电介质（24），以最小化电容耦合和传播延迟问题。 根据一个实施例的低K电介质包括封盖电介质，其用于防止相邻金属导体上的腐蚀，并且当导体被图案化时用作蚀刻停止层。 封盖电介质进一步最小化所得到的层间和层间电介质结构的内在应力。

公开(公告)号：WO1997047034A1

公开(公告)日：1997-12-11

申请号：PCT/US1997002503

申请日：1997-02-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  BRENNAN, William, S. ,  DAWSON, Robert ,  FULFORD, H., Jim, Jr. ,  HAUSE, Fred, N. ,  BANDYOPADHYAY, Basab ,  MICHAEL, Mark, W.

IPC: H01L21/768

CPC classification number: H01L21/76877

Abstract: A multilevel interconnect structure is provided. The multilevel interconnect structure includes two, three or more levels of conductors formed according to at least two exemplary embodiments. According to one embodiment, the contact structure which links conductors (12) on one level to an underlying level is formed by a single via etch step followed by a fill step separate from a fill step used in filling the via. In this embodiment, the via (24) is filled with a conductive material (30) which forms a plug separate from the material (14) used in forming the interconnect. In another exemplary embodiment, the step used in filling the via can be the same as that used in forming the interconnect. In either instance, a via is formed through a first dielectric (22) to underlying conductors. A second dielectric (36) is patterned upon the first dielectric and serves to laterally bound the fill material used in producing the overlying interconnect. Regardless of the process sequence chosen, the interlevel dielectric structure (36) is left substantially planar in readiness for subsequent interconnect levels dielectrically deposited thereon.

Abstract translation: 提供了多层互连结构。 多层互连结构包括根据至少两个示例性实施例形成的两层，三层或更多级的导体。 根据一个实施例，通过单个通孔蚀刻步骤形成将一个层上的导体（12）连接到下面的层的接触结构，随后是与用于填充通孔的填充步骤分离的填充步骤。 在该实施例中，通孔（24）填充有形成与用于形成互连件的材料（14）分开的插头的导电材料（30）。 在另一个示例性实施例中，用于填充通孔的步骤可以与在形成互连中使用的步骤相同。 在任一情况下，通过第一电介质（22）到底层导体形成通孔。 第二电介质（36）在第一电介质上被图案化，并且用于横向地限制用于制造上覆互连的填充材料。 不管所选择的工艺顺序如何，层间电介质结构（36）保持基本平坦，以便随后在其上介电沉积的互连层。