公开(公告)号：WO2004023533A3

公开(公告)日：2004-03-18

申请号：PCT/US2003/027366

申请日：2003-08-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： LUNING, Scott ,  WIECZOREK, Karsten ,  KAMMLER, Thorsten

IPC: H01L21/336

Abstract: An insulated gate semiconductor device (100) having reduced gate resistance and a method for manufacturing the semiconductor device (100). A gate structure (112) is formed on a major surface (104) of a semiconductor substrate (102). Successive nitride spacers (118, 128) are formed adjacent the sidewalls of the gate structure (112). The nitride spacers (118, 128) are etched and recessed using a single etch to expose the upper portions (115A, 117A) of the gate structure (112). Source (132) and drain (134) regions are formed in the semiconductor substrate (102). Silicide regions (140, 142, 144) are formed on the top surface (109) and the exposed upper portions (115A, 117A) of the gate structure (112) and the source region (132) and the drain region (134). Electrodes (150, 152, 154) are formed in contact with the silicide (140, 142, 144) of the respective gate structure (112), source region (132), and the drain region (134).

公开(公告)号：WO2003079424A1

公开(公告)日：2003-09-25

申请号：PCT/US2002/041089

申请日：2002-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WIECZOREK, Karsten ,  HORSTMANN, Manfred ,  STEPHAN, Rolf

IPC: H01L21/28

CPC classification number: H01L21/823443 ,  H01L21/823418 ,  H01L29/665

Abstract: A method is disclosed in which differing metal layers are sequentially deposited on silicon-containing regions so that the type and thickness of the metal layers may be adapted to specific characteristics of the underlying silicon-containing regions. Subsequently, a heat treatment is performed to convert the metals into metal silicides so as to improve the electrical conductivity of the silicon-containing regions. In this way, silicide portions may be formed that are individually adapted to specific silicon-containing regions so that device performance of individual semiconductor elements or the overall performance of a plurality of semiconductor elements may be significantly improved. Moreover, a semiconductor device is disclosed comprising at least two silicon-containing regions having formed therein differing silicide portions, wherein at least one silicide portion comprises a noble metal.

Abstract translation: 公开了一种方法，其中不同的金属层依次沉积在含硅区域上，使得金属层的类型和厚度可以适应于下面的含硅区域的特定特性。 随后，进行热处理以将金属转化为金属硅化物，从而提高含硅区域的导电性。 以这种方式，可以形成独立地适应特定的含硅区域的硅化物部分，从而可以显着改善各个半导体元件的器件性能或多个半导体元件的整体性能。 此外，公开了一种半导体器件，其包括至少两个其中形成有不同硅化物部分的含硅区域，其中至少一个硅化物部分包括贵金属。

公开(公告)号：WO2003075326A2

公开(公告)日：2003-09-12

申请号：PCT/US2002/041142

申请日：2002-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： STEPHAN, Rolf ,  HORSTMANN, Manfred ,  WIECZOREK, Karsten

IPC: H01L21/00

CPC classification number: H01L21/324 ,  H01L21/28052 ,  H01L21/823835 ,  H01L21/823842

Abstract: In a method for fabricating a semiconductor device different types of a metal-semiconductor compound (241, 261) are formed on or in at least two different conductive semiconductor regions so that for each semiconductor region the metal-semiconductor compound region may be formed to obtain an optimum overall performance of the semiconductor device. On one of the two semiconductor regions, the metal-semiconductor compound is formed of at least two different metal layers (240, 260), whereas the metal-semiconductor compound in or on the other semiconductor region is formed from a single metal layer (240).

Abstract translation: 在制造半导体器件的方法中，在至少两个不同的导电半导体区域上形成不同类型的金属 - 半导体化合物（241,261），使得对于每个半导体区域，可以形成金属 - 半导体化合物区域以获得 半导体器件的最佳整体性能。 在两个半导体区域中的一个上，金属 - 半导体化合物由至少两个不同的金属层（240,260）形成，而另一个半导体区域中或另一个半导体区域中的金属 - 半导体化合物由单个金属层（240 ）。

公开(公告)号：EP1523775A2

公开(公告)日：2005-04-20

申请号：EP03748928.3

申请日：2003-06-24

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： WIECZOREK, Karsten ,  HORSTMANN, Manfred ,  KRUEGER, Christian

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/78696 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78684

Abstract: An SOI transistor element and a method of fabricating the same is disclosed, wherein a high concentration of stationary point defects is created by including a region within the active transistor area that has a slight lattice mismatch. In one particular embodiment, a silicon germanium layer 320 is provided in the active area having a high concentration of point defects due to relaxing the strain of the silicon germanium layer upon heat treating the transistor element. Due to the point defects, the recombination rate is significantly increased, thereby reducing the number of charged carriers stored in the active area.

公开(公告)号：EP1245045A1

公开(公告)日：2002-10-02

申请号：EP00952341.6

申请日：2000-07-31

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HORSTMANN, Manfred ,  WIECZOREK, Karsten ,  BURBACH, Gert

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5222 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L2924/0002 ,  H01L2924/00

Abstract: There is provided a semiconductor device comprising an insulating layer (108) which is partly formed of porous material, and a method for fabricating the device. A stray capacitance of adjacent wiring lines is significantly reduced by reducing the amount of material, i.e., by using porous material in the insulating layer (108) of a metallization layer. In one embodiment, the porous layer (108) may be fabricated separately on a further substrate and is subsequently transferred to the product wafer while the further substrate and the product wafer are appropriately aligned to each other. In this way, fabrication of complete metallization layers having a reduced dielectric constant in advance or concurrently with the product wafer carrying the MOS structure is possible. Due to the reduced capacitance of the wiring lines of the metallization layer, signal performance and/or power consumption of an integrated circuit is improved.

公开(公告)号：EP1649506A1

公开(公告)日：2006-04-26

申请号：EP04754333.5

申请日：2004-06-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WIECZOREK, Karsten ,  FEUDEL, Thomas ,  KAMMLER, Thorsten ,  BUCHHOLTZ, Wolfgang

IPC: H01L21/336 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/66553 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/78618

Abstract: By forming an implantation mask (220) prior to the definition of the drain and the source areas (208), an effective decoupling of the gate dopant concentration from that of the drain and source concentrations is achieved. Moreover, after removal of the implantation mask (220), the lateral dimension of the gate electrode (205) may be defined by well-established sidewall spacer (207) techniques, thereby providing a scaling advantage with respect to conventional approaches based on photolithography and anisotropic etching.

公开(公告)号：EP1565934A1

公开(公告)日：2005-08-24

申请号：EP03786592.0

申请日：2003-11-06

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： FEUDEL, Thomas ,  HORSTMANN, Manfred ,  WIECZOREK, Karsten ,  KRUEGEL, Stephan

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/225

CPC classification number: H01L29/6659 ,  H01L21/2253 ,  H01L29/665 ,  H01L29/7833

Abstract: High-k dielectric spacer elements on the gate electrode of a field effects transistor in combination with an extension region that is formed by dopant diffusion from the high-k spacer elements into the underlying semiconductor region provides for an increased charge carrier density in the extension region. In this way, the limitation of the charge carrier density to approximately the solid solubility of dopants in the extension region may be overcome, thereby allowing extremely shallow extension regions without unduly compromising the transistor performance.

公开(公告)号：EP1523775B1

公开(公告)日：2013-07-31

申请号：EP03748928.3

申请日：2003-06-24

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WIECZOREK, Karsten ,  HORSTMANN, Manfred ,  KRUEGER, Christian

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78684

公开(公告)号：EP1488461A1

公开(公告)日：2004-12-22

申请号：EP02807162.9

申请日：2002-12-20

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： WIECZOREK, Karsten ,  HORSTMANN, Manfred ,  STEPHAN, Rolf

IPC: H01L29/36 ,  H01L29/78 ,  H01L21/336 ,  H01L21/8232

CPC classification number: H01L21/823807 ,  H01L29/1033 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/6659

Abstract: An epitaxially grown channel layer is provided on a well structure after ion implantation steps and heat treatment steps are performed to establish a required dopant profile in the well structure. The channel layer may be undoped or slightly doped, as required, so that the finally obtained dopant concentration in the channel layer is significantly reduced compared to a conventional device to thereby provide a retrograde dopant profile in a channel region of a field effect transistor. Additionally, a barrier diffusion layer may be provided between the well structure and the channel layer to reduce up-diffusion during any heat treatments carried out after the formation of the channel layer. The final dopant profile in the channel region may be adjusted by the thickness of the channel layer, the thickness and the composition of the diffusion barrier layer and any additional implantation steps to introduce dopant atoms in the channel layer.

公开(公告)号：EP1476899A1

公开(公告)日：2004-11-17

申请号：EP02787067.4

申请日：2002-12-20

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： WIECZOREK, Karsten ,  GRAETSCH, Falk ,  KRUEGEL, Stephan

IPC: H01L21/311 ,  H01L21/318 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/314

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/518

Abstract: A method of forming oxide layers of different thickness on a substrate (1) is disclosed, wherein the oxide layers preferably serve as gate insulation layers of field effect transistors. The method allows to form very thin, high quality oxide layers with a reduced number of masking steps compared to the conventional processing, wherein the thickness difference can be maintained within a range of some tenths of a nanometer. The method substantially eliminates any high temperature oxidations and is also compatible with most chemical vapor deposition techniques used for gate dielectric deposition in sophisticated semiconductor devices