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    DOPED REGIONS IN AN SOI SUBSTRATE
    21.
    发明公开
    DOPED REGIONS IN AN SOI SUBSTRATE 审中-公开
    掺杂区在硅绝缘体上的硅衬底

    公开(公告)号：EP1514310A1

    公开(公告)日：2005-03-16

    申请号：EP03731587.6

    申请日：2003-05-28

    Applicant: ADVANCED MICRO DEVICES INC.

    Inventor： WRISTERS, Derick, J. ,  WEI, Andy, C. ,  FUSELIER, Mark, B.

    IPC: H01L27/12 ,  H01L21/84

    CPC classification number: H01L27/1203 ,  H01L21/84

    Abstract: In one illustrative embodiment, the method comprises providing an SOI substrate (30) comprises of an active layer (30C), a buried insulation layer (30B) and a bulk substrate (30A), forming a doped region (34) in the bulk substrate (30A) under the active layer, forming a plurality of transistors (32) above the SOI substrate in an area above the doped region (34) and applying a voltage to the doped region to vary a threshold voltage of at least one of the plurality of transistors. In another illustrative embodiment, the method comprises providing a consumer product comprised of at least one integrated circuit product (64), the integrated circuit product being comprised of a plurality of transistors (32) formed in an active layer (30C) of an SOI substrate (30) above a doped region (34) formed in a bulk substrate (30A) of the SOI substrate, the doped region (34) being formed under the active layer, sensing an activity level of the integrated circuit product (64) and applying a voltage of magnitude and a polarity to the doped region, the magnitude and polarity of the applied voltage being determined based upon the sensed activity level of the integrated circuit product (64).

    SEMICONDUCTOR DEVICE FORMED OVER A MULTIPLE THICKNESS BURIED OXIDE LAYER, AND METHODS OF MAKING SAME
    22.
    发明公开
    SEMICONDUCTOR DEVICE FORMED OVER A MULTIPLE THICKNESS BURIED OXIDE LAYER, AND METHODS OF MAKING SAME 审中-公开
    半导体器件上制成的多厚度掩埋氧化物层BEEN AND METHOD FOR THEIR

    公开(公告)号：EP1490900A1

    公开(公告)日：2004-12-29

    申请号：EP02792406.7

    申请日：2002-12-17

    Applicant: ADVANCED MICRO DEVICES INC.

    Inventor： FUSELIER, Mark, B. ,  WRISTERS, Derick, J. ,  WEI, Andy, C.

    IPC: H01L21/762 ,  H01L21/335 ,  H01L21/316

    CPC classification number: H01L29/66772 ,  H01L21/26533 ,  H01L21/76243 ,  H01L29/78648

    Abstract: The present invention is generally directed to a semiconductor device formed over a multiple thickness buried oxide layer 20, and various methods of making same. In one illustrative embodiment, the device comprises a bulk substrate 12, a multiple thickness buried oxide layer 20 formed above the bulk substrate 12, and an active layer 21 formed above the multiple thickness buried oxide layer 20, the semiconductor device being formed in the active layer 21 above the multiple thickness buried oxide layer 20. In some embodiments, the multiple thickness buried oxide layer 20 is comprised of a first section 20B positioned between two second sections 20A, the first section 20B having a thickness that is less than the thickness of the second sections 20A. In one illustrative embodiment, the method comprises performing a first oxygen ion implant process 42 on a silicon substrate 40, forming a masking layer 44 above the substrate 40, performing a second oxygen ion implant process 46 on the substrate 40 through the masking layer 44, and performing at least one heating process on the substrate 40 to form a multiple thickness buried oxide layer 20 in the substrate 40. In another illustrative embodiment, the method comprises performing a first oxygen ion implant process 46 on a silicon substrate 40, forming a masking layer 44 above the substrate 40, performing a second oxygen ion implant process 42 on the substrate through the masking layer 44, and performing at least one heating process on the substrate 40 to form a multiple thickness buried oxide layer 20 in the substrate 40. In yet another illustrative embodiment, the method comprises forming a multiple thickness buried oxide layer 20 using a wafer bonding technique.

    METHOD OF FORMING A LOCAL INTERCONNECT
    23.
    发明公开
    METHOD OF FORMING A LOCAL INTERCONNECT 有权
    处理本地连接

    公开(公告)号：EP1070348A1

    公开(公告)日：2001-01-24

    申请号：EP98955236.9

    申请日：1998-11-02

    Applicant: ADVANCED MICRO DEVICES INC.

    Inventor： DAWSON, Robert ,  GARDNER, Mark, I. ,  HAUSE, Frederick, N. ,  FULFORD, H., Jim, Jr. ,  MICHAEL, Mark, W. ,  MOORE, Bradley, T. ,  WRISTERS, Derick, J.

    IPC: H01L21/768

    CPC classification number: H01L21/76895

    Abstract: A local interconnect (LI) structure (112) is formed by forming a silicide layer (60, 50) in selected regions of a semiconductor structure then depositing an essentially uniform layer (110) of transition or refractory metal overlying the semiconductor structure. The metal local interconnect (112) is deposited without forming an intermediate insulating layer between the silicide (60, 50) and metal layers (110) to define contact openings or vias. In some embodiments, titanium is a suitable metal for formation of the local interconnect (112). Suitable selected regions (60) for silicide layer formation include, for example, silicided source/drain (S/D) regions and silicided gate contact regions (50). The silicided regions form uniform structures for electrical coupling to underlying doped regions that are parts of one or more semiconductor devices. In integrated circuits in which an etch-stop layer (100) is desired for the patterning of the metal film, a first optional insulating layer (100) is deposited prior to deposition of the metal film. In one example, the insulating layer is a silicon dioxide (oxide) layer that is typically less than 10 nm in thickness.

    METHOD OF MAKING NMOS AND PMOS DEVICES WITH REDUCED MASKING STEPS
    24.
    发明授权
    METHOD OF MAKING NMOS AND PMOS DEVICES WITH REDUCED MASKING STEPS 失效
    用于NMOS和PMOS器件具有减少掩模步骤

    公开(公告)号：EP0978141B1

    公开(公告)日：2006-07-12

    申请号：EP98912999.4

    申请日：1998-03-19

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： HAUSE, Frederick, N. ,  DAWSON, Robert ,  FULFORD, H., Jim ,  GARDNER, Mark, I. ,  MICHAEL, Mark, W. ,  MOORE, Bradley, T. ,  WRISTERS, Derick, J.

    IPC: H01L21/8238

    CPC classification number: H01L21/823814

    Abstract: A method of making NMOS and PMOS devices with reduced masking steps is disclosed. The method includes providing a semiconductor substrate with a first active region of first conductivity type and a second active region of second conductivity type, forming a gate material over the first and second active regions, forming a first masking layer over the gate material, etching the gate material using the first masking layer as an etch mask to form a first gate over the first active region and a second gate over the second active region, implanting a dopant of second conductivity type into the first and second active regions using the first masking layer as an implant mask, forming a second masking layer that covers the first active region and includes an opening above the second active region, and implanting a dopant of first conductivity type into the second active region using the first and second masking layers as an implant mask. Advantageously, the dopant of first conductivity type counterdopes the dopant of second conductivity type in the second active region, thereby providing source and drain regions of second conductivity type in the first active region and source and drain regions of first conductivity type in the second active region with a single masking step and without subjecting either gate to dopants of first and second conductivity type.

    METHOD OF MAKING AN SOI SEMICONDUCTOR DEVICE HAVING ENHANCED, SELF-ALIGNED DIELECTRIC REGIONS IN THE BULK SILICON SUBSTRATE
    25.
    发明公开
    METHOD OF MAKING AN SOI SEMICONDUCTOR DEVICE HAVING ENHANCED, SELF-ALIGNED DIELECTRIC REGIONS IN THE BULK SILICON SUBSTRATE 审中-公开
    方法用于生产具有自调节INCREASED介质区域的SOI半导体部件在硅衬底上

    公开(公告)号：EP1509950A2

    公开(公告)日：2005-03-02

    申请号：EP03731586.8

    申请日：2003-05-28

    Applicant: ADVANCED MICRO DEVICES INC.

    Inventor： WEI, Andy, C. ,  WRISTERS, Derick, J. ,  FUSELIER, Mark, B.

    IPC: H01L21/762 ,  H01L21/84 ,  H01L27/12

    CPC classification number: H01L29/66772 ,  H01L29/78603

    Abstract: In one illustrative embodiment, the method comprises forming a gate electrode 34 above an SOI substrate 30 comprised of a bulk substrate, a buried insulation layer 30B and an active layer 30C, the gate electrode 34 having a protective layer 34A formed thereabove, and forming a plurality of dielectric regions 45 in the bulk substrate 30 after the gate electrode 34 is formed, the dielectric regions 45 being self-aligned with respect to the gate electrode 34, the dielectric regions 45 having a dielectric constant that is less than a dielectric constant of the bulk substrate 30A. In further embodiments, the method comprises forming a gate electrode 34 above an SOI substrate 30 comprised of bulk substrate 30A, a buried insulation layer 30B and an active layer 30C, the gate electrode 34 having the protective layer 34A formed thereabove, performing at least one oxygen implant process after the gate electrode 34 and the protective layer 34A are formed to introduce oxygen atoms into the bulk substrate 30A to thereby form a plurality of oxygen-doped regions 52 in the bulk substrate 30A, and performing at least one anneal process to convert the oxygen-doped regions 52 to dielectric regions 45 comprised of silicon dioxide in the bulk substrate 30A. In one illustrative embodiment, the device comprises a gate electrode 34 formed above an SOI structure 30 comprised of a bulk substrate 30A, a buried insulation layer 30B, and an active layer 30C, and a plurality of dielectric regions 45 comprised of silicon dioxide formed in the bulk substrate 30A, the dielectric regions 45 being self-aligned with respect to the gate electrode 34.

    BIASED, TRIPLE-WELL FULLY DEPLETED SOI STRUCTURE, AND VARIOUS METHODS OF MAKING AND OPERATING SAME
    27.
    发明公开
    BIASED, TRIPLE-WELL FULLY DEPLETED SOI STRUCTURE, AND VARIOUS METHODS OF MAKING AND OPERATING SAME 有权
    LOADED，总贫困TRIPLE SINK SOI结构和不同工艺生产同样与功能

    公开(公告)号：EP1488463A1

    公开(公告)日：2004-12-22

    申请号：EP02797394.0

    申请日：2002-12-17

    Applicant: ADVANCED MICRO DEVICES INC.

    Inventor： WEI, Andy, C. ,  WRISTERS, Derick, J. ,  FUSELIER, Mark, B.

    IPC: H01L29/786

    CPC classification number: H01L29/78648 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78609

    Abstract: In one illustrative embodiment, the device comprises a transistor (32) formed above a silicon-on-insulator substrate (30) comprised of a bulk substrate (30A), a buried insulation layer (30B) and an active layer (30C), the bulk substrate (30A) being doped with a first type of dopant material and a first well (50) formed in the bulk substrate (30A), the first well (50) being doped with a second type of dopant material that is of a type opposite the first type of dopant material. The device further comprises a second well (52) formed in the bulk substrate (30A) within the first material, the transistor (32) being formed in the active layer (30C) above the second well (52) an electrical contact (60) for the first well (50) and an electrical contact (62) for said second well (52). In one illustrative embodiment, a method of forming a transistor (32) above a silicon-on-insulator substrate (30) comprisedof a bulk substrate (30A) a buried oxide layer (30B) and an active layer (30C), the bulk substrate (30A) being doped with a first type of dopant material is disclosed. The method comprises performing a first ion implant process using a dopant material that is of a type opposite the first type of dopant material to form a first well region (50) within the bulk substrate (30A), performing a second ion implant process using a dopant material that is the same type as the first type of dopant material to form a second well region (52) in the bulk substrate (30A) within the first well (50), the transistor (32) being formed in the active layer (30C) above the second well (52), forming a conductive contact (60) to the first well (50) and forming a conductive contact to the second well (60). The method further comprises a contact well (58) formed in the bulk substrate (30A) within the first well (50), the contact well (58) being comprised of a dopant material that is of the same type as the second type of dopant material, the contact well (58) within the first well (50) having a dopant concentration that is greater than a dopant concentration of the first well (50).

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