公开(公告)号：US09053952B2

公开(公告)日：2015-06-09

申请号：US13631769

申请日：2012-09-28

Applicant: Apple Inc.

Inventor： Shawn X. Arnold ,  Matthew E. Last

IPC: H01L29/02 ,  H01L21/78 ,  H01L21/762 ,  H01L29/06 ,  H01L21/683 ,  H01L21/822

CPC classification number: H01L29/0657 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L21/822 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: One embodiment for forming a shaped substrate for an electronic device can form a shaped perimeter to define the substrate shape on the surface of a substrate. The shaped perimeter can extend at least part way into the substrate. A subsequent thinning process can remove substrate material and expose the shaped perimeter effectively forming shaped dies from the substrate.

Abstract translation: 用于形成用于电子器件的成形衬底的一个实施例可以形成成形周边以限定衬底表面上的衬底形状。 成形的周边可以至少部分地延伸到基底中。 随后的变薄过程可以去除衬底材料并且使形状的周边有效地从衬底形成成形的模具。

公开(公告)号：US09018091B2

公开(公告)日：2015-04-28

申请号：US14252596

申请日：2014-04-14

Applicant: Apple Inc.

Inventor： Shawn X. Arnold ,  Terry L. Gilton ,  Matthew E. Last

IPC: H01L21/4763 ,  G06K9/00 ,  H01L23/00 ,  H01L29/06 ,  H01L23/24

CPC classification number: H05K1/183 ,  G06F1/16 ,  G06F3/041 ,  G06K9/00053 ,  H01L23/24 ,  H01L24/11 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L24/85 ,  H01L29/0657 ,  H01L2224/43 ,  H01L2224/45015 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48479 ,  H01L2224/85 ,  H01L2224/85051 ,  H01L2224/85186 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10253 ,  H05K1/111 ,  H05K2201/09036 ,  H05K2201/10151 ,  H01L2924/20752 ,  H01L2224/48471 ,  H01L2224/4554

Abstract: Various methods for forming a low profile assembly are described. The low profile assembly may include an integrated circuit. The integrated circuit as well as components associated with the integrated circuit may be positioned below a surface plane of a printed circuit board in which the integrated circuit is located. The integrated circuit may include bond wires configured to electrically connect the integrated circuits to other components. The low profile assembly may include forming various layers over a substrate and later removing some of the layers.

Abstract translation: 描述了用于形成低轮廓组件的各种方法。 薄型组件可以包括集成电路。 集成电路以及与集成电路相关的部件可以位于集成电路所在的印刷电路板的表面的下方。 集成电路可以包括配置成将集成电路电连接到其他部件的接合线。 薄型组件可以包括在衬底上形成各种层并且随后去除一些层。

公开(公告)号：US20140218155A1

公开(公告)日：2014-08-07

申请号：US14163852

申请日：2014-01-24

Applicant: Apple Inc.

Inventor： Sunil M. Akre ,  Shawn X. Arnold

IPC: H01F27/29 ,  H01F27/24 ,  H05K3/30 ,  H01F27/02

CPC classification number: H05K1/141 ,  H05K1/144 ,  H05K1/165 ,  H05K1/185 ,  H05K2201/086 ,  Y10T29/4913

Abstract: Embedded PCB (printed circuit board) is used for the packaging and assembly of a low profile power conversion system module that can be employed in space constrained environment of small computer/electronic systems. The low profile power conversion system module includes an embedded PCB, a power silicon device embedded within the PCB, a magnetic component which is either embedded within the PCB or disposed on the PCB, and input/output terminals disposed on the side of the embedded PCB. The embedded PCB and the magnetic component are thin planar shaped to save vertical space. The low profile power conversion system module can be placed inside a cavity formed in the system PCB to save even more vertical space.

Abstract translation: 嵌入式PCB（印刷电路板）用于封装和组装小型电力转换系统模块，可用于小型计算机/电子系统的空间受限的环境中。 低剖面功率转换系统模块包括嵌入式PCB，嵌入PCB内的功率硅器件，嵌入在PCB内或布置在PCB上的磁性部件，以及设置在嵌入式PCB侧面的输入/输出端子 。 嵌入式PCB和磁性元件是薄平面形状，以节省垂直空间。 低功率转换系统模块可以放置在系统PCB中形成的腔内，以节省更多的垂直空间。

公开(公告)号：US20140134760A1

公开(公告)日：2014-05-15

申请号：US14162577

申请日：2014-01-23

Applicant: Apple Inc.

Inventor： Shawn X. Arnold ,  Dennis R. Pyper

IPC: H01L21/66 ,  H01L23/00

CPC classification number: H01L22/10 ,  H01L23/48 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/58 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L24/82 ,  H01L29/84 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82105 ,  H01L2224/82138 ,  H05K1/00 ,  H05K1/0268 ,  H05K1/186 ,  H05K3/4611 ,  H05K2201/10674 ,  H05K2203/063

Abstract: Methods and devices for embedding semiconductors in printed circuit boards (PCBs) are provided. In one example, a method of manufacturing a PCB having a die assembly embedded therein includes removing a release film from an adhesive layer of the die assembly. The method also includes disposing the die assembly on a first layer of the PCB such that the adhesive layer contacts the first layer of the PCB. The method includes disposing a second layer of the PCB over the first layer such that the die assembly is within an intermediate portion between the first layer and the second layer. The method also includes filling the intermediate portion with resin and subjecting the PCB to a press cycle to cure the resin.

Abstract translation: 提供了在印刷电路板（PCB）中嵌入半导体的方法和装置。 在一个示例中，制造具有嵌入其中的模具组件的PCB的方法包括从模具组件的粘合剂层去除脱模膜。 该方法还包括将模具组件设置在PCB的第一层上，使得粘合剂层接触PCB的第一层。 该方法包括在第一层上布置PCB的第二层，使得模具组件位于第一层和第二层之间的中间部分内。 该方法还包括用树脂填充中间部分，并对PCB进行加压循环以固化树脂。

公开(公告)号：US10179254B2

公开(公告)日：2019-01-15

申请号：US15086813

申请日：2016-03-31

Applicant: Apple Inc.

Inventor： Paul A. Martinez ,  Jason C. Sauers ,  Shawn X. Arnold

IPC: H01G4/30 ,  A62C31/22 ,  H01G4/12 ,  H05K1/18 ,  A62C33/04 ,  F16L5/04 ,  H01G4/38 ,  H01G4/012 ,  H01G4/232 ,  A62C31/02 ,  E06B5/16

Abstract: This application relates to capacitors that resist deformation because of the configuration of their conductive and dielectric layers. The capacitors are multilayer capacitors that include multiple dielectric and conductive layers. The dielectric layers can be arranged in a way that creates a rigid barrier or dead zone, which can resist mechanical deformation when the multilayer capacitor is charged. In some embodiments, two or more multilayer capacitors are stacked together in an arrangement that causes each of the multilayer capacitors to cancel any deformations of the other when the multilayer capacitors are charged. In this way, noise exhibited by the multilayer capacitors can be reduced.

公开(公告)号：US20180061578A1

公开(公告)日：2018-03-01

申请号：US15694726

申请日：2017-09-01

Applicant: Apple Inc.

Inventor： Gang Ning ,  Paul A. Martinez ,  Amanda R. Rainer ,  Won Seop Choi ,  Gemin Li ,  Zhong-Qing Gong ,  Shawn X. Arnold

IPC: H01G4/30 ,  H01G4/008 ,  H01G4/232 ,  H01G4/12 ,  H05K1/18

CPC classification number: H01G4/30 ,  H01G2/065 ,  H01G4/008 ,  H01G4/012 ,  H01G4/1209 ,  H01G4/232 ,  H05K1/18 ,  H05K3/284 ,  H05K2201/0133 ,  H05K2201/10015

Abstract: Passive component structures that may save space, are readily manufactured, and are easy to use. In one example, a passive component structure may include two capacitors, each formed as a group of plates separate and apart from the other. The two groups of plates may have a spacing layer between them.

公开(公告)号：US09763329B1

公开(公告)日：2017-09-12

申请号：US15068474

申请日：2016-03-11

Applicant: Apple Inc.

Inventor： Anne M. Mason ,  Peter J. Johnston ,  Christine A. Laliberte ,  Dominic P. McCarthy ,  Shawn X. Arnold ,  Souvik Mukherjee

IPC: H05K7/10 ,  H05K1/18 ,  H05K1/11 ,  H05K1/02 ,  H05K3/40 ,  H05K3/30

CPC classification number: H01L23/5386 ,  H01C7/00 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/17 ,  H01L25/18 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2924/1434 ,  H01L2924/19043 ,  H05K1/113 ,  H05K1/167 ,  H05K1/181 ,  H05K3/3436 ,  H05K3/4076 ,  H05K2201/096 ,  H05K2201/10159 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y02P70/613

Abstract: A circuit board includes conductive traces being sandwiched by an upper insulating layer and a lower insulating layer, a first array of conductive vias extending perpendicularly to the conductive traces, the vias in the first array of conductive vias being arranged such that any two adjacent vias in a row of vias extending along any given dimension in the first array of conductive vias are equally spaced from each other, and isolation resistors embedded within the first array of conductive vias such that each isolation resistor is disposed between at least two adjacent vias in the first array of conductive vias, each isolation resistor being disposed closer to the conductive via to which the isolation resistor is coupled than all other conductive vias surrounding the isolation resistor.

公开(公告)号：US09402316B2

公开(公告)日：2016-07-26

申请号：US14696327

申请日：2015-04-24

Applicant: Apple Inc.

Inventor： Shawn X. Arnold ,  Terry L. Gilton ,  Matthew E. Last

IPC: H01L23/48 ,  H05K1/18 ,  H01L29/06 ,  G06K9/00 ,  H01L23/00 ,  G06F1/16 ,  G06F3/041 ,  H05K1/11 ,  H01L23/24

CPC classification number: H05K1/183 ,  G06F1/16 ,  G06F3/041 ,  G06K9/00053 ,  H01L23/24 ,  H01L24/11 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L24/85 ,  H01L29/0657 ,  H01L2224/43 ,  H01L2224/45015 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48479 ,  H01L2224/85 ,  H01L2224/85051 ,  H01L2224/85186 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10253 ,  H05K1/111 ,  H05K2201/09036 ,  H05K2201/10151 ,  H01L2924/20752 ,  H01L2224/48471 ,  H01L2224/4554

Abstract: Various methods for forming a low profile assembly are described. The low profile assembly may include an integrated circuit. The integrated circuit as well as components associated with the integrated circuit may be positioned below a surface plane of a printed circuit board in which the integrated circuit is located. The integrated circuit may include bond wires configured to electrically connect the integrated circuits to other components. The low profile assembly may include forming various layers over a substrate and later removing some of the layers.

公开(公告)号：US09117873B2

公开(公告)日：2015-08-25

申请号：US13629560

申请日：2012-09-27

Applicant: Apple Inc.

Inventor： Shawn X. Arnold ,  Matthew E. Last

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/02 ,  H01L23/12 ,  H01L21/762 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L29/06

CPC classification number: H01L21/762 ,  H01L23/498 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/26 ,  H01L25/0655 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/06183 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/14183 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/81141 ,  H01L2224/83141 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/10156 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A direct multiple substrate die assembly can include a first and a second substrate, wherein each substrate can include at least one interlocking edge feature. An electrical interconnection area can be formed adjacent to or within the interlocking edge feature on each substrate and can be configured to couple one or more electrical signals between the substrates. In one embodiment, the interlocking edge feature can include one or more keying features that can enable accurate alignment between the substrates. In yet another embodiment, the direct multiple substrate die assembly can be mounted out of plane with respect to a supporting substrate.

Abstract translation: 直接多基板模具组件可以包括第一和第二基板，其中每个基板可以包括至少一个互锁边缘特征。 电互连区域可以形成在每个基板上的互锁边缘特征附近或内部，并且可以被配置为在基板之间耦合一个或多个电信号。 在一个实施例中，互锁边缘特征可以包括能够实现基板之间的精确对准的一个或多个键控特征。 在另一个实施例中，直接多基板模具组件可以相对于支撑基板安装在平面外。

公开(公告)号：US08809859B2

公开(公告)日：2014-08-19

申请号：US14162577

申请日：2014-01-23

Applicant: Apple Inc.

Inventor： Shawn X. Arnold ,  Dennis R. Pyper

IPC: H01L23/58 ,  H01L27/15 ,  H01L23/04 ,  H01L21/00 ,  H05K1/00 ,  H01L23/48 ,  H01L29/84 ,  H01L21/66 ,  H01L23/00

CPC classification number: H01L22/10 ,  H01L23/48 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/58 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L24/82 ,  H01L29/84 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82105 ,  H01L2224/82138 ,  H05K1/00 ,  H05K1/0268 ,  H05K1/186 ,  H05K3/4611 ,  H05K2201/10674 ,  H05K2203/063

Abstract: Methods and devices for embedding semiconductors in printed circuit boards (PCBs) are provided. In one example, a method of manufacturing a PCB having a die assembly embedded therein includes removing a release film from an adhesive layer of the die assembly. The method also includes disposing the die assembly on a first layer of the PCB such that the adhesive layer contacts the first layer of the PCB. The method includes disposing a second layer of the PCB over the first layer such that the die assembly is within an intermediate portion between the first layer and the second layer. The method also includes filling the intermediate portion with resin and subjecting the PCB to a press cycle to cure the resin.

Abstract translation: 提供了在印刷电路板（PCB）中嵌入半导体的方法和装置。 在一个示例中，制造具有嵌入其中的模具组件的PCB的方法包括从模具组件的粘合剂层去除脱模膜。 该方法还包括将模具组件设置在PCB的第一层上，使得粘合剂层接触PCB的第一层。 该方法包括在第一层上布置PCB的第二层，使得模具组件位于第一层和第二层之间的中间部分内。 该方法还包括用树脂填充中间部分，并对PCB进行加压循环以固化树脂。