公开(公告)号：US20230378044A1

公开(公告)日：2023-11-23

申请号：US18109337

申请日：2023-02-14

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chin-Tang Hsieh ,  Lung-Hua Ho ,  Chih-Ming Kuo ,  Chun-Ting Kuo ,  Yu-Hui Hu ,  Chih-Hao Chiang ,  Chen-Yu Wang ,  Kung-An Lin ,  Pai-Sheng Cheng

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13014 ,  H01L2224/16227

Abstract: A flip-chip bonding structure includes a substrate and a chip. A lead of the substrate includes a body, a hollow opening, a bonding island and at least one connecting bridge. The hollow opening is in the body and surrounded by the body. The bonding island is located in the hollow opening such that there is a hollow space in the hollow opening and located between the body and the bonding island. The connecting bridge is located in the hollow space to connect the body and the bonding island. A bump of the chip is bonded to the bonding island by a solder. The solder is restricted on the bonding island and separated from the body by the hollow space so as to avoid the solder from overflowing to the body and avoid the chip from shifting.

公开(公告)号：US20230187378A1

公开(公告)日：2023-06-15

申请号：US17988846

申请日：2022-11-17

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Shrane-Ning Jenq ,  Chen-Yu Wang ,  Chin-Tang Hsieh ,  Shu-Yeh Chang ,  Lung-Hua Ho

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L23/3121 ,  H01L23/49811 ,  H01L21/561

Abstract: In a method of manufacturing a semiconductor package, at least one conductive wire is formed on a substrate in a wire bonding process, a ball end of the conductive wire is located above the substrate, a molding material is provided to cover the conductive wire except the ball end, and an EMI shielding layer is formed on the molding material to connect to the ball end. Owing to the ball end is exposed on the molding material, connection area of the EMI shielding layer to the conductive wire is increased to improve connection strength and reliability between the EMI shielding layer and the conductive wire.

公开(公告)号：US08772644B2

公开(公告)日：2014-07-08

申请号：US13644709

申请日：2012-10-04

Applicant: Chipbond Technology Corporation

Inventor： Chih-Ming Kuo ,  Lung-Hua Ho ,  You-Ming Hsu

IPC: H05K1/16

CPC classification number: H01L23/5223 ,  H01G4/01 ,  H01L28/86 ,  H01L2924/0002 ,  H05K1/162 ,  H01L2924/00

Abstract: A carrier with three-dimensional capacitor includes a substrate and a three-dimensional capacitor, wherein the substrate comprises a trace layer having a first terminal and a second terminal. The three-dimensional capacitor is integrally formed as one piece with the trace layer. The three-dimensional capacitor and the trace layer are made of same material. The three-dimensional capacitor comprises a first capacitance portion and a second capacitance portion, the first capacitance portion comprises a first section, a second section and a first passage, the second capacitance portion is formed at the first passage. The second capacitance portion comprises a third section, a fourth section and a second passage communicated with the first passage. The first capacitance portion is located at the second passage, a first end of the first capacitance portion connects to the first terminal, and a third end of the second capacitance portion connects to the second terminal.

Abstract translation: 具有三维电容器的载体包括基板和三维电容器，其中所述基板包括具有第一端子和第二端子的迹线层。 三维电容器与轨迹层一体形成。 三维电容器和迹线层由相同的材料制成。 三维电容器包括第一电容部分和第二电容部分，第一电容部分包括第一部分，第二部分和第一通道，第二电容部分形成在第一通道处。 第二电容部分包括与第一通道连通的第三部分，第四部分和第二通道。 第一电容部分位于第二通道处，第一电容部分的第一端连接到第一端子，第二电容部分的第三端连接到第二端子。