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公开(公告)号：DE69731366D1
公开(公告)日：2004-12-02
申请号：DE69731366
申请日：1997-12-30
Applicant: COMPAQ COMPUTER CORP
Inventor： HARESKI PATRICIA E , WALKER WILLIAM J , KOTZUR GARY B , MAYER DALE J , WITKOWSKI MICHAEL L
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公开(公告)号：DE69027348T2
公开(公告)日：1997-01-02
申请号：DE69027348
申请日：1990-01-19
Applicant: COMPAQ COMPUTER CORP
Inventor： ABDOO DAVID G , MAYER DALE J
IPC: G06F12/06
Abstract: An adder (204,206,208) and a comparator (242) form portions of a modular memory address block determination circuit. The starting address of the first block and the enable signal of the first block are added to produce the starting address of the second block. This procedure is repeated for each block. The determined starting address for each block is compared with the requested memory address and, unless the block is inhibited or disabled, if equal a signal indicates a match. The circuit is used on a circuit board which emulates three conventionally separate memory circuit boards. The registers for each emulated circuit board are provided and appropriate bus signals are developed.
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公开(公告)号：JPH10210070A
公开(公告)日：1998-08-07
申请号：JP36153697
申请日：1997-12-26
Applicant: COMPAQ COMPUTER CORP
Inventor： WALKER WILLIAM J , KOTZUR GARY B , WITKOWSKI MICHAEL L , HARESKI PATRICIA E , MAYER DALE J
Abstract: PROBLEM TO BE SOLVED: To efficiently judge the receiving state and transmitting state of the port of a network switch by periodically polling each port state logic of plural network ports for receiving a state signal. SOLUTION: A multi-port poling system is provided with plural network ports 104 and 110. Each port includes a port state logic for supplying a port state signal indicating whether or not the corresponding port receives data from a network device and whether or not the corresponding port has an available space for receiving data for transmitting the data to the network device. The switch manager of a network switch 102 includes a poling logic for periodically poling the port state logic of each port for receiving the state signal, and a memory for storing a value indicating the state signal to each port. Then, the receiving and tramsmitting state of each port is maintained in a memory.
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公开(公告)号：JPH10210069A
公开(公告)日：1998-08-07
申请号：JP36077397
申请日：1997-12-26
Applicant: COMPAQ COMPUTER CORP
Inventor： WITKOWSKI MICHAEL L , GREGORY T CHANDLER , MUHAMMAD A KAN , KOTZUR GARY B , MAYER DALE J , WALKER WILLIAM J
Abstract: PROBLEM TO BE SOLVED: To provide a network switch which has a capability of processing of a network traffic in a heavy load. SOLUTION: This network switch 102 includes plural first network ports, plural second network ports, a first bus, a second bus, and a bridge interface connected between first and second busses. First ports receive and transit network data in accordance with a first network protocol, and second ports receive and transmit network data in accordance with a second network protocol. First and second busses are operated in accordance with different bus standards. The bridge interface allows data transfer between first and second busses, namely, between networks operated in accordance with different protocols.
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公开(公告)号：JPH1097509A
公开(公告)日：1998-04-14
申请号：JP22340397
申请日：1997-08-20
Applicant: COMPAQ COMPUTER CORP
Inventor： OLARIG SOMPONG P , MAYER DALE J , WHITEMAN WILLIAM F
IPC: G06F15/16 , G06F9/46 , G06F13/24 , G06F15/177
Abstract: PROBLEM TO BE SOLVED: To compensate the delivery of balanced interrupts to processors by providing a plurality of local programmable interrupt controllers arranged on respective programmable interruption controller bus and a central programmable interruption controller. SOLUTION: The respective processors, CPU 105 (106), for example, are connected to the corresponding local programmable interrupt controllers, LOPIC 305 (306), for example. Respective LOPIC 305 and 306 process interrupts delivery protocol and the corresponding processors. Respective LOPIC, LOPIC 305 (306), for example, are connected to the central programmable interrupt controller COPIC 312 through the programmable interrupt controller bus 311. COPIC 312 is connected to a plurality of I/O sources and gives the functions of I/O interruption routing and the masking/arbitration of interrupts.
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Patent Agency Ranking
公开(公告)号：DE69735575T2
公开(公告)日：2006-08-24
申请号：DE69735575
申请日：1997-08-13
Applicant: COMPAQ COMPUTER CORP
Inventor： MAYER DALE J , OLARIG SOMPONG P , WHITEMAN WILLIAM F , HEINRICH DAVID F
IPC: G06F13/18 , G06F13/24 , G06F13/362
Abstract: A method for supporting multiple distributed interrupt controllers, designated as bus agents, in a symmetric multiprocessing system, includes the steps of assigning a unique identification number to each bus agent, receiving bus requests from the bus agents over four data lines in groups of four, and granting bus ownership to a selected one of the requesting bus agents. Similarly, a computer system that supports multiple distributed interrupt controllers, designated as bus agents, in a symmetric multiprocessing system, includes structure for assigning a unique identification number to each bus agent, four data lines for receiving bus requests from the bus agents in groups of four, and structure for granting bus ownership to a selected one of the requesting bus agents.
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公开(公告)号：DE69735575D1
公开(公告)日：2006-05-18
申请号：DE69735575
申请日：1997-08-13
Applicant: COMPAQ COMPUTER CORP
Inventor： MAYER DALE J , OLARIG SOMPONG P , WHITEMAN WILLIAM F , HEINRICH DAVID F
IPC: G06F13/18 , G06F13/24 , G06F13/362
Abstract: A method for supporting multiple distributed interrupt controllers, designated as bus agents, in a symmetric multiprocessing system, includes the steps of assigning a unique identification number to each bus agent, receiving bus requests from the bus agents over four data lines in groups of four, and granting bus ownership to a selected one of the requesting bus agents. Similarly, a computer system that supports multiple distributed interrupt controllers, designated as bus agents, in a symmetric multiprocessing system, includes structure for assigning a unique identification number to each bus agent, four data lines for receiving bus requests from the bus agents in groups of four, and structure for granting bus ownership to a selected one of the requesting bus agents.
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公开(公告)号：DE69732086D1
公开(公告)日：2005-02-03
申请号：DE69732086
申请日：1997-12-30
Applicant: COMPAQ COMPUTER CORP
Inventor： MAYER DALE J , RICHTER ROGER , WITKOWSKI MICHAEL L , KOTZUR GARY B , HARESKI PATRICIA E , WALKER WILLIAM J
Abstract: A network switch including a central memory that stores device identification information, port numbers, control information, and packet data received at the ports of the switch. The memory includes a packet section that stores packet data and a device identification section that stores identification entries, where each entry corresponds to a network device coupled to a port of the switch. The switch includes a switch manager to control data flow between the ports and the central memory. Each of the identification entries includes a unique network address to identify one of the network devices and a port number to identify one of the network ports. Each of the identification entries is located within the central memory at a hash address derived by hashing the unique network address. Hash logic receives and hashes each network address to determine a hash address, which is used to access the identification entries. The memory is organized into a chain structure to enable quick access of entries. The switch manager further includes a control memory for storing control registers, including a freepool control register for identifying a freepool chain of memory sectors, a receive control register for identifying a corresponding receive sector chain and a transmit control register for identifying a corresponding transmit packet chain for each of the ports.
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公开(公告)号：DE69027348D1
公开(公告)日：1996-07-18
申请号：DE69027348
申请日：1990-01-19
Applicant: COMPAQ COMPUTER CORP
Inventor： ABDOO DAVID G , MAYER DALE J
IPC: G06F12/06
Abstract: An adder (204,206,208) and a comparator (242) form portions of a modular memory address block determination circuit. The starting address of the first block and the enable signal of the first block are added to produce the starting address of the second block. This procedure is repeated for each block. The determined starting address for each block is compared with the requested memory address and, unless the block is inhibited or disabled, if equal a signal indicates a match. The circuit is used on a circuit board which emulates three conventionally separate memory circuit boards. The registers for each emulated circuit board are provided and appropriate bus signals are developed.
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公开(公告)号：AU5297093A
公开(公告)日：1994-04-26
申请号：AU5297093
申请日：1993-09-29
Applicant: COMPAQ COMPUTER CORP
Inventor： CULLEY PAUL R , LANDRY JOHN A , MAYER DALE J , WANNER CHRISTOPHER C , MCSWAIN GUY E
Abstract: An arrangement of direct memory access (DMA), interrupt and timer functions in a multiprocessor computer system to allow symmetrical processing. Several functions which are considered common to all of the CPUs and those which are conveniently accessed through an expansion bus remain in a central system peripheral chip coupled to the expansion bus. These central functions include the primary portions of the DMA controller and arbitration circuitry to control access of the expansion bus. A distributed peripheral, including a programmable interrupt controller, multiprocessor interrupt logic, nonmaskable interrupt logic, local DMA logic and timer functions, is provided locally for each CPU. A bus is provided between the central and distributed peripherals to allow the central peripheral to broadcast information to the CPUs, and to provide local information from the distributed chip to the central peripheral when the local CPU is programming or accessing functions in the central peripheral.
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