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公开(公告)号：BRPI0505156A
公开(公告)日：2006-07-11
申请号：BRPI0505156
申请日：2005-11-23
Applicant: GEN ELECTRIC
Inventor： STEVANOVIC LJUBISA DRAGOLJUB , DELGADO ELADIO CLEMENTE , SCHUTTEN MICHAEL JOSEPH , BEAUPRE RICHARD ALFRED , ROOIJ MICHAEL ANDREW DE
IPC: H01H37/00
Abstract: A power module (10) includes a substrate (12) that includes an upper layer (16), an electrical insulator and a thermal coupling layer. The upper layer includes an electrically conductive pattern (17) and is configured for receiving power devices (14). The electrical insulator is disposed between the upper layer and the thermal coupling layer. The thermal coupling layer is configured for thermal coupling to a heat sink. The power module further includes at least one laminar interconnect (18) that includes first and second electrically conductive layers (20, 24) and an insulating layer (22) disposed between the first and second electrically conductive layers. The first electrically conductive layer of the laminar interconnect is electrically connected to the upper layer of the substrate. Electrical connections (42) connect a top side (19) of the power devices to the second electrically conductive layer of the laminar interconnect.
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公开(公告)号：CA2780658C
公开(公告)日：2019-08-06
申请号：CA2780658
申请日：2012-06-22
Applicant: GEN ELECTRIC
Inventor： BEAUPRE RICHARD ALFRED , SMOLENSKI JOSEPH LUCIAN , GERSTLER WILLIAM DWIGHT , SHEN XIAOCHUN
IPC: H01L23/367 , H05K7/20
Abstract: A cooling device for a power module having an electronic module disposed on a base plate via a substrate is disclosed. The cooling device includes a heat sink plate having at least one cooling segment. The cooling segment includes an inlet plenum for entry of a cooling medium, a plurality of inlet manifold channels, a plurality of outlet manifold channels, and an outlet plenum. The plurality of inlet manifold channels are coupled orthogonally to the inlet plenum for receiving the cooling medium from the inlet plenum. The plurality of outlet manifold channels are disposed parallel to the inlet manifold channels. The outlet plenum is coupled orthogonally to the plurality of outlet manifold channels for exhaust of the cooling medium. A plurality of millichannels are disposed in the base plate orthogonally to the inlet and the outlet manifold channels. The plurality of milli channels direct the cooling medium from the plurality of inlet manifold channels to the plurality of outlet manifold channels.
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公开(公告)号：CA2768534C
公开(公告)日：2019-06-18
申请号：CA2768534
申请日：2012-02-16
Applicant: GEN ELECTRIC
Inventor： BEAUPRE RICHARD ALFRED , SMOLENSKI JOSEPH LUCIAN
Abstract: A busbar (10) for power conversion applications that includes two planar conductors (20, 30) that have terminal locations (22, 32); a first planar insulator (40) located between the planar conductors (20, 30); two impedances elements (24, 34) that are electrically connected to each of the planar conductors (20, 30), wherein the impedance elements (24, 34) each extend in a plane that is non-coplanar from the planar conductors (20, 30), further wherein the impedance elements (24, 34) are configured so as to define a gap (50) between them; and a second planar insulator (45) is located in the gap (50). The present invention has been described in terms of specific embodiment(s), and it is recognized that equivalents, alternatives, and modifications, aside from those expressly stated, are possible and within the scope of the appending claims.
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Patent Agency Ranking
公开(公告)号：BRPI1004830A2
公开(公告)日：2013-02-19
申请号：BRPI1004830
申请日：2010-10-19
Applicant: GEN ELECTRIC
IPC: H01L23/538
Abstract: A device is provided that includes a first conductive substrate (102) and a second conductive substrate (104). A first power semiconductor component (118a) having a first thickness can be electrically coupled to the first conductive substrate. A second power semiconductor component (118b) having a second thickness can be electrically coupled to the second conductive substrate. A positive terminal (142) can also be electrically coupled to the first conductive substrate, while a negative terminal (144) can be electrically coupled to the second power semiconductor component, and an output terminal (146) may be electrically coupled to the first power semiconductor component and the second conductive substrate. The terminals, the power semiconductor components, and the conductive substrates may thereby be incorporated into a common circuit loop, and may together be configured such that a width of the circuit loop in at least one direction is defined by at least one of the first thickness or the second thickness.
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公开(公告)号：CA2719179A1
公开(公告)日：2011-04-30
申请号：CA2719179
申请日：2010-10-28
Applicant: GEN ELECTRIC
Abstract: A device is provided that includes a first conductive substrate (102) and a second conductive substrate (104). A first power semiconductor component (118a) having a first thickness can be electrically coupled to the first conductive substrate. A second power semiconductor component (118b) having a second thickness can be electrically coupled to the second conductive substrate. A positive terminal (142) can also be electrically coupled to the first conductive substrate, while a negative terminal (144) can be electrically coupled to the second power semiconductor component, and an output terminal (146) may be electrically coupled to the first power semiconductor component and the second conductive substrate. The terminals, the power semiconductor components, and the conductive substrates may thereby be incorporated into a common circuit loop, and may together be configured such that a width of the circuit loop in at least one direction is defined by at least one of the first thickness or the second thickness.
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公开(公告)号：DE102010017001A1
公开(公告)日：2010-12-02
申请号：DE102010017001
申请日：2010-05-18
Applicant: GEN ELECTRIC
IPC: H01L23/473 , H01L23/36 , H05K7/20
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公开(公告)号：CA2563480A1
公开(公告)日：2007-04-26
申请号：CA2563480
申请日：2006-10-12
Applicant: GEN ELECTRIC
Inventor： BEAUPRE RICHARD ALFRED , DELGADO ELADIO CLEMENTE
Abstract: A power circuit package (10) includes a base (12) including a substrate (14) , a plurality of interconnect circuit layers (16) over the substrate with each including a substrate insulating layer (18) patterned with substrate electrical interconnects (20), and via connections (22, 24) extending from a top surface of the substrate t o at least one of the substrate electrical interconnects (20); and a power semiconducto r module (26) including power semiconductor devices (28) each including device pads (30) on a top surface of the respective power semiconductor device and backside contacts (31) on a bottom surface of the respective power semiconductor device, the power semiconductor devices being coupled to a membrane structure (32), the membra ne structure including a membrane insulating layer (34) and membrane electrical interconnects (36) over the membrane insulating layer and selectively extending to the device pads, wherein the backside contacts (31) are coupled to selected substrate electrical interconnects or via connections.
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公开(公告)号：CA2555394A1
公开(公告)日：2007-02-17
申请号：CA2555394
申请日：2006-08-03
Applicant: GEN ELECTRIC
Inventor： WOJNAROWKSI ROBERT JOHN , FILLION RAYMOND ALBERT , KORMAN CHARLES STEVEN , ELASSER AHMED , BEAUPRE RICHARD ALFRED
IPC: H01L23/02 , H01L21/70 , H01L21/768 , H01L23/055 , H01L23/48
Abstract: A semiconductor chip packaging structure comprising a dielectric film 1 0 having one or more through holes 11 aligned with the one or more contact pad s 22 and 23 of at least one power semiconductor chip 21. A patterned electrically conductive layer 40 adjacent to the dielectric film 10 has one or more electrically conductive posts 41 which extend through the one or more though holes 11 aligned with the contact pads 22 and 23 to electrically couple the conductive layer 40 to the contact pads 22 and 23. In certain embodiments, one or more air gaps 91 may be formed betwee n the dielectric film 10 and the active surface 24 of the at least one power semiconductor chip 21. Methods for fabricating the semiconductor chip packaging structure are also disclosed.
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