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公开(公告)号：WO2008076985B1
公开(公告)日：2008-08-28
申请号：PCT/US2007087801
申请日：2007-12-17
Applicant: WOJNAROWSKI ROBERT JOHN , GEN ELECTRIC , BERKAN ERTUGRUL , ANDARAWIS EMAD ANADARAWIS , SEALING CHARLES SCOTT , SEELY CHARLES SCOTT , DELGADO ELADIO CLEMENTE , HAYS DAVID CECIL , KAPUSTA CHRISTOPHER JAMES , GRUBER NANETTE JUDITH
Inventor： BERKAN ERTUGRUL , ANDARAWIS EMAD ANADARAWIS , SEALING CHARLES SCOTT , SEELY CHARLES SCOTT , DELGADO ELADIO CLEMENTE , HAYS DAVID CECIL , KAPUSTA CHRISTOPHER JAMES , GRUBER NANETTE JUDITH
IPC: H01L27/20 , G01N29/14 , G01N29/22 , H01L41/04 , H01L41/113
CPC classification number: H01L27/20 , G01M5/00 , G01N29/245 , G01N29/2475 , G01N2291/0231 , H01L41/047 , H01L41/1132
Abstract: A piezoelectric planar composite apparatus (30, 30') to provide health monitoring of a structure and associated methods are provided. The piezoelectric planar composite apparatus (30, 30') includes a piezoelectric electric material layer (41, 41'), multiple electrodes (35, 35') positioned in electrical contact with the piezoelectric material layer (41, 41'), and multiple sets of electrode interconnect conductors (53) each positioned in electrical contact with a different subset of the of the electrodes (35, 35') and positioned to form multiple complementary electrode patterns. Each of the complementary electrode patterns is positioned to form an electric field having an electric field axis oriented along a different physical axis from that of an electric field formed by at least one other of the complementary electrode patterns. The interconnect conductors (53) can be distributed over several electrode interconnect conductor carrying layers (51) to enhance formation of the different complementary electrode patterns.
Abstract translation: 提供了一种用于提供对结构和相关方法的健康监测的压电平面复合设备（30,30'）。 压电平面复合设备（30,30'）包括压电电材料层（41,41'），定位成与压电材料层（41,41'）电接触的多个电极（35,35'），以及多个 电极互连导体组（53），每个电极互连导体定位成与电极（35,35'）的不同子集电接触并定位以形成多个互补电极图案。 互补电极图案中的每一个被定位为形成电场，该电场具有沿着与由互补电极图案中的至少一个另外的互补电极图案形成的电场不同的物理轴定向的电场轴。 互连导体（53）可以分布在几个电极互连导体承载层（51）上以增强不同互补电极图案的形成。
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公开(公告)号：WO2004038468A3
公开(公告)日：2004-06-17
申请号：PCT/US0333279
申请日：2003-10-20
Applicant: GEN ELECTRIC
Inventor： SAIA RICHARD JOSEPH , GORCZYCA THOMAS BERT , KAPUSTA CHRISTOPHER JAMES , BALCH ERNEST WAYNE , CLAYDON GLENN SCOTT , DASGUPTA SAHMITA , DELGADO ELADIO CLEMENTE
CPC classification number: G02B6/122 , G02B6/12002 , G02B6/12004 , G02B6/1221 , G02B6/138 , G02B6/42 , H01L2224/04105 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2924/15153 , H01L2924/15192
Abstract: An optoelectronic package is fabricated by a method which includes: positioning an optical device within a window of a substrate activeside up and below a top substrate surface; filling the window with an optical polymer material; planarizing surfaces of the optical polymer material and the substrate; patterning waveguide material over the optical polymer material and the substrate to form an optical interconnection path and to form a mirror to reflect light from the optical device to the interconnection path; and forming a via to expose a bond pad of the optical device.
Abstract translation: 一种光电子封装通过包括以下步骤的方法制造：将光学器件定位在衬底有源面的窗口内上和下顶部衬底表面; 用光学聚合物材料填充窗口; 平坦化光学聚合物材料和基底的表面; 在所述光学聚合物材料和所述衬底上形成波导材料以形成光学互连路径并且形成反射镜以将来自所述光学器件的光反射到所述互连路径; 以及形成通孔以暴露光学器件的接合焊盘。
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公开(公告)号：CA2563480C
公开(公告)日：2016-02-02
申请号：CA2563480
申请日：2006-10-12
Applicant: GEN ELECTRIC
Inventor： DELGADO ELADIO CLEMENTE , BEAUPRE RICHARD ALFRED
Abstract: A power circuit package (10) includes a base (12) including a substrate (14), a plurality of interconnect circuit layers (16) over the substrate with each including a substrate insulating layer (18) patterned with substrate electrical interconnects (20), and via connections (22, 24) extending from a top surface of the substrate to at least one of the substrate electrical interconnects (20); and a power semiconductor module (26) including power semiconductor devices (28) each including device pads (30) on a top surface of the respective power semiconductor device and backside contacts (31) on a bottom surface of the respective power semiconductor device, the power semiconductor devices being coupled to a membrane structure (32), the membrane structure including a membrane insulating layer (34) and membrane electrical interconnects (36) over the membrane insulating layer and selectively extending to the device pads, wherein the backside contacts (31) are coupled to selected substrate electrical interconnects or via connections.
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公开(公告)号：CA2836351A1
公开(公告)日：2014-06-19
申请号：CA2836351
申请日：2013-12-12
Applicant: GEN ELECTRIC
Inventor： DELGADO ELADIO CLEMENTE , GLASER JOHN STANLEY , ROWDEN BRIAN LYNN
IPC: H01L23/46
Abstract: An integrated power module (10) includes a substantially planar insulated metal substrate (12) having at least one cut-out region (18); at least one substantially planar ceramic substrate (14) disposed within the cut-out region, wherein the ceramic substrate is framed on at least two sides by the insulated metal substrate, the ceramic substrate including a first metal layer (15) on a first side and a second metal layer (17) on a second side; at least one power semiconductor device (20) coupled to the first side of the ceramic substrate; at least one control device (22) coupled to a first surface of the insulated metal substrate; a power overlay (60) electrically connecting the at least one semiconductor power device and the at least one control device; and a cooling fluid reservoir (58) operatively connected to the second metal layer of the at least one ceramic substrate, wherein a plurality of cooling fluid passages (54) are provided in the cooling fluid reservoir.
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公开(公告)号：CA2719179C
公开(公告)日：2013-08-13
申请号：CA2719179
申请日：2010-10-28
Applicant: GEN ELECTRIC
Abstract: A device is provided that includes a first conductive substrate (102) and a second conductive substrate (104). A first power semiconductor component (118a) having a first thickness can be electrically coupled to the first conductive substrate. A second power semiconductor component (118b) having a second thickness can be electrically coupled to the second conductive substrate. A positive terminal (142) can also be electrically coupled to the first conductive substrate, while a negative terminal (144) can be electrically coupled to the second power semiconductor component, and an output terminal (146) may be electrically coupled to the first power semiconductor component and the second conductive substrate. The terminals, the power semiconductor components, and the conductive substrates may thereby be incorporated into a common circuit loop, and may together be configured such that a width of the circuit loop in at least one direction is defined by at least one of the first thickness or the second thickness.
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Patent Agency Ranking
公开(公告)号：DE60321702D1
公开(公告)日：2008-07-31
申请号：DE60321702
申请日：2003-10-20
Applicant: GEN ELECTRIC
Inventor： SAIA RICHARD JOSEPH , GORCZYCA THOMAS BERT , KAPUSTA CHRISTOPHER JAMES , BALCH ERNEST WAYNE , CLAYDON GLENN SCOTT , DASGUPTA SAHMITA , DELGADO ELADIO CLEMENTE
Abstract: An optoelectronic package is fabricated by a method which includes: positioning an optical device within a window of a substrate active-side up and below a top substrate surface; filling the window with an optical polymer material; planarizing surfaces of the optical polymer material and the substrate; patterning waveguide material over the optical polymer material and the substrate to form an optical interconnection path; and to form a mirror to reflect light from the optical device to the interconnection path; and forming a via to expose a bond pad of the optical device.
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公开(公告)号：AU2003284300A1
公开(公告)日：2004-05-13
申请号：AU2003284300
申请日：2003-10-20
Applicant: GEN ELECTRIC
Inventor： SAIA RICHARD JOSEPH , GORCZYCA THOMAS BERT , KAPUSTA CHRISTOPHER JAMES , BALCH ERNEST WAYNE , CLAYDON GLENN SCOTT , DASGUPTA SAHMITA , DELGADO ELADIO CLEMENTE
Abstract: An optoelectronic package is fabricated by a method which includes: positioning an optical device within a window of a substrate active-side up and below a top substrate surface; filling the window with an optical polymer material; planarizing surfaces of the optical polymer material and the substrate; patterning waveguide material over the optical polymer material and the substrate to form an optical interconnection path; and to form a mirror to reflect light from the optical device to the interconnection path; and forming a via to expose a bond pad of the optical device.
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公开(公告)号：BR102013032665A2
公开(公告)日：2016-03-15
申请号：BR102013032665
申请日：2013-12-18
Applicant: GEN ELECTRIC
Inventor： ROWDEN BRIAN LYNN , DELGADO ELADIO CLEMENTE , GLASER JOHN STANLEY
IPC: H01L23/02
Abstract: módulo de potência integrado e método de fabricação de um módulo de potência trata-se de um módulo de potência integrado (10) que inclui um substrato de metal isolado substancialmente plano (12) que tem pelo menos uma região recortada (18); pelo menos um substrato cerâmico substancialmente plano (14) disposto dentro da região de recorte, em que o substrato cerâmico é armado em pelo menos dois lados pelo substrato de metal isolado, sendo que o substrato cerâmico inclui uma primeira camada de metal (15) em um primeiro lado e uma segunda camada de metal (17) em um segundo lado pelo menos um dispositivo semicondutor de potência (20) acoplado ao primeiro lado do substrato cerâmico; pelo menos um dispositivo de controle (22) acoplado a uma primeira superfície do substrato de metal isolado; um revestimento de potência (60) que conecta eletricamente o pelo menos um dispositivo de potência de semicondutor e o pelo menos um dispositivo de controle; e um reservatório de fluido de resfriamento (58) conectado de modo operacional à segunda camada de metal do pelo menos um substrato cerâmico, em que uma pluralidade de passagens de fluido de resfriamento (54) é fornecida no reservatório de fluido de resfriamento.
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公开(公告)号：BRPI1004830A2
公开(公告)日：2013-02-19
申请号：BRPI1004830
申请日：2010-10-19
Applicant: GEN ELECTRIC
IPC: H01L23/538
Abstract: A device is provided that includes a first conductive substrate (102) and a second conductive substrate (104). A first power semiconductor component (118a) having a first thickness can be electrically coupled to the first conductive substrate. A second power semiconductor component (118b) having a second thickness can be electrically coupled to the second conductive substrate. A positive terminal (142) can also be electrically coupled to the first conductive substrate, while a negative terminal (144) can be electrically coupled to the second power semiconductor component, and an output terminal (146) may be electrically coupled to the first power semiconductor component and the second conductive substrate. The terminals, the power semiconductor components, and the conductive substrates may thereby be incorporated into a common circuit loop, and may together be configured such that a width of the circuit loop in at least one direction is defined by at least one of the first thickness or the second thickness.
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公开(公告)号：CA2719179A1
公开(公告)日：2011-04-30
申请号：CA2719179
申请日：2010-10-28
Applicant: GEN ELECTRIC
Abstract: A device is provided that includes a first conductive substrate (102) and a second conductive substrate (104). A first power semiconductor component (118a) having a first thickness can be electrically coupled to the first conductive substrate. A second power semiconductor component (118b) having a second thickness can be electrically coupled to the second conductive substrate. A positive terminal (142) can also be electrically coupled to the first conductive substrate, while a negative terminal (144) can be electrically coupled to the second power semiconductor component, and an output terminal (146) may be electrically coupled to the first power semiconductor component and the second conductive substrate. The terminals, the power semiconductor components, and the conductive substrates may thereby be incorporated into a common circuit loop, and may together be configured such that a width of the circuit loop in at least one direction is defined by at least one of the first thickness or the second thickness.
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