中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

21 records (took 0.019 seconds)

    POWER DISTRIBUTION SYSTEM INCLUDING MATRIX FILTER
    2.
    发明专利
    POWER DISTRIBUTION SYSTEM INCLUDING MATRIX FILTER 失效

    公开(公告)号：JPH10271681A

    公开(公告)日：1998-10-09

    申请号：JP33922297

    申请日：1997-12-10

    Applicant: GEN ELECTRIC

    Inventor： RAMAKRISHNAN SRIRAM ,  STEIGERWALD ROBERT LOUIS ,  KORMAN CHARLES STEVEN

    IPC: H02J1/02 ,  H02M1/12 ,  H02M1/14 ,  H02M3/00

    Abstract: PROBLEM TO BE SOLVED: To attenuate the high frequency noise by arranging capacitors alternately with the output buses of converters within the first plane, and lining up inductors with the capacitors and the output buses of the converters positioned among these inductors, within the second plane orthogonal to the first plane. SOLUTION: A power converter 12 receives power from an adjusting power source, and converts the adjusted input voltage into many output voltages small in ripple, low in noise, and precise in degree of adjustment. An output matrix filter 14 is utilized for each output of the power converter 12, and besides a local matrix filter 16 is utilized for the entry point near each load 18. For example, the power converter 13 has three outputs, and each output is coupled with its relevant output matrix filter 14, and the power is distributed to load 18 through a distribution bus 20 of low noise. Hereby, a low-noise power distribution system can be achieved.

    POWER SEMICONDUCTOR PACKAGING METHOD AND STRUCTURE
    3.
    发明专利
    POWER SEMICONDUCTOR PACKAGING METHOD AND STRUCTURE 未知

    公开(公告)号：CA2555394C

    公开(公告)日：2016-02-23

    申请号：CA2555394

    申请日：2006-08-03

    Applicant: GEN ELECTRIC

    Inventor： FILLION RAYMOND ALBERT ,  BEAUPRE RICHARD ALFRED ,  ELASSER AHMED ,  WOJNAROWKSI ROBERT JOHN ,  KORMAN CHARLES STEVEN

    IPC: H01L23/02 ,  H01L21/70 ,  H01L21/768 ,  H01L23/055 ,  H01L23/48

    Abstract: A semiconductor chip packaging structure comprising a dielectric film 10 having one or more through holes 11 aligned with the one or more contact pads 22 and 23 of at least one power semiconductor chip 21. A patterned electrically conductive layer 40 adjacent to the dielectric film 10 has one or more electrically conductive posts 41 which extend through the one or more though holes 11 aligned with the contact pads 22 and 23 to electrically couple the conductive layer 40 to the contact pads 22 and 23. In certain embodiments, one or more air gaps 91 may be formed between the dielectric film 10 and the active surface 24 of the at least one power semiconductor chip 21. Methods for fabricating the semiconductor chip packaging structure are also disclosed.

    Diode bridge for rapid transfer of current includes direct assembly with bus bars to minimise inductance and resistance
    4.
    发明专利
    Diode bridge for rapid transfer of current includes direct assembly with bus bars to minimise inductance and resistance 未知

    公开(公告)号：FR2797359A1

    公开(公告)日：2001-02-09

    申请号：FR0007032

    申请日：2000-05-31

    Applicant: GEN ELECTRIC

    Inventor： KORMAN CHARLES STEVEN ,  PARK JOHN NORTON ,  CLOCK ALLEN WILLIAM ,  AKSIT MAHMUT FARUK

    IPC: H01H9/54 ,  H02M7/06 ,  H01H33/59

    Abstract: The diodes are integrated with the bus bars to minimise losses arising from inductance and resistance. The configuration of diode bridge and bus bar comprises at least four diodes (1,2,3,4) placed between the cathode and anode contacts. A further assembly forming the bars comprises at least two bus bars (44,45) and a bus bar contact, each bus bar and each contact having an interval between them in the open position, whilst each bus bar and contact conduct current in the closed position. The diode bridge is integrated into the assembly forming the bus bars in order to minimise the inductance and the resistance between them. The diode bridge may be integrated into the assembly forming the bus bars in a symmetrical bridge arrangement, or in a lateral bridge arrangement. The structure forms part of a hybrid circuit breaker (10) with a mechanical switch (12) and an energy control circuit (20).

    Integral AC module grounding system
    5.
    发明专利
    Integral AC module grounding system 未知

    公开(公告)号：AU2011204837A1

    公开(公告)日：2012-02-16

    申请号：AU2011204837

    申请日：2011-07-19

    Applicant: GEN ELECTRIC

    Inventor： KORMAN CHARLES STEVEN ,  JOHNSON NEIL ANTHONY

    IPC: H01L31/042 ,  H02M1/00 ,  H02M7/00

    Abstract: INTEGRAL AC MODULE GROUNDING SYSTEM 100441 A photovoltaic (PV) ac-module grounding system includes a plurality of PV dc-voltage modules. Each PV dc-voltage module is integrated with a corresponding dc-ac micro-inverter to provide a corresponding PV ac-voltage module. Each PV ac-voltage module includes an ac-voltage plug and play connector that includes a dc ground conductor. Each dc-ac micro-inverter is internally electrically connected to its own chassis ground or metal enclosure which in turn is electrically connected to a corresponding dc ground conductor. A dc ground path is carried through an ac power bus from ac-voltage module to ac-voltage module through the plug and play connectors via the dc ground conductors.

    6.
    发明专利
    未知

    公开(公告)号：BR0301047A

    公开(公告)日：2004-08-17

    申请号：BR0301047

    申请日：2003-05-02

    Applicant: GEN ELECTRIC

    Inventor： GAO GUANZHONG ,  REED CLIVE W ,  KORMAN CHARLES STEVEN ,  HERD KENNETH G

    IPC: G01R31/00 ,  G01R31/12 ,  G01R31/02

    Abstract: A monitoring system includes at least one partial discharge (PD) sensor. The PD sensor is configured to monitor a component of an aircraft wiring system and to acquire a monitoring signal. A method embodiment for monitoring an aircraft wiring system includes acquiring a number of monitoring signals for a number of components of the aircraft wiring system using a number of partial discharge PD sensors. The method further includes conveying the monitoring signals from at least one of the PD sensors to a data acquisition system.

    7.
    发明专利
    未知

    公开(公告)号：FR2839366A1

    公开(公告)日：2003-11-07

    申请号：FR0305423

    申请日：2003-05-02

    Applicant: GEN ELECTRIC

    Inventor： GAO GUANZHONG ,  REED CLIVE WILLIAM ,  KORMAN CHARLES STEVEN ,  HERD KENNETH G

    IPC: G01R31/00 ,  G01R31/12 ,  G01R31/08

    Abstract: A monitoring system includes at least one partial discharge (PD) sensor. The PD sensor is configured to monitor a component of an aircraft wiring system and to acquire a monitoring signal. A method embodiment for monitoring an aircraft wiring system includes acquiring a number of monitoring signals for a number of components of the aircraft wiring system using a number of partial discharge PD sensors. The method further includes conveying the monitoring signals from at least one of the PD sensors to a data acquisition system.

    High-frequency superconductive inductor for a power conversion system
    8.
    发明专利
    High-frequency superconductive inductor for a power conversion system 未知

    公开(公告)号：GB2272111A

    公开(公告)日：1994-05-04

    申请号：GB9322494

    申请日：1993-11-01

    Applicant: GEN ELECTRIC

    Inventor： ROSHEN WASEEM AHMED ,  MOGRO-CAMPERO ANTONIO ALBERTO ,  BRAY JAMES WILLIAM ,  KORMAN CHARLES STEVEN

    IPC: H01F6/06 ,  H01F5/08

    Abstract: An inductor (10) uses high temperature superconductive material in order to obtain high Q for high frequency operation. The superconductive material is applied as thin film (16F) to substrate (12F or 12S) Conductive films (14F, 14S) may be applied to the outside of the inductor in order to shield against leakage of the magnetic field. The conductive films (14F, 14S) may be of superconductive material. The inductor may be formed with plural superconductive layers (16F, 16S). The superconductive films may be applied to opposite sides of the same substrate. The inductor may be connected to a capacitor to realize a resonant circuit for use in a power conversion system.

    Sistema de paneles solares desplegables
    9.
    发明专利
    Sistema de paneles solares desplegables 未知

    公开(公告)号：ES2401985T3

    公开(公告)日：2013-04-26

    申请号：ES11161942

    申请日：2011-04-11

    Applicant: GEN ELECTRIC

    Inventor： KORMAN CHARLES STEVEN ,  JOHNSON NEIL ANTHONY

    IPC: F24J2/36 ,  F24J2/52 ,  H01L31/048 ,  H02S30/20

    Abstract: Un sistema (300) de paneles solares desplegables que comprende una pluralidad de paneles (200) de célulassolares que están mecánica y eléctricamente acoplados entre sí, en el que los diversos paneles (200) de célulassolares están mecánicamente acoplados entre sí mediante un conjunto (301) de bisagra de forma que la pluralidadde paneles (200) de células solares puede ser plegada en una disposición de apilamiento para su expedición, ydesplegadas durante la instalación; caracterizado porque el sistema comprende ademásal menos un canal (308) de montaje con al menos una abertura (310) para recibir un miembro (311) de sujeción, yun miembro (313) de pie que se extiende entre dos paneles adyacentes de la pluralidad de paneles (200) de célulassolares, estando el miembro (313) de pie adaptado para ser recibido dentro del canal (308) de montaje, incluyendoel miembro de pie una abertura (315) para recibir dicho miembro (311) de sujeción insertado dentro de una aberturaseleccionada de la al menos una abertura (310) del canal (308) de montaje para la instalación de la pluralidad depaneles (200) de células solares en un ángulo (A1, A2) de inclinación deseado.

    POWER SEMICONDUCTOR PACKAGING METHOD AND STRUCTURE
    10.
    发明专利
    POWER SEMICONDUCTOR PACKAGING METHOD AND STRUCTURE 未知

    公开(公告)号：CA2555394A1

    公开(公告)日：2007-02-17

    申请号：CA2555394

    申请日：2006-08-03

    Applicant: GEN ELECTRIC

    Inventor： WOJNAROWKSI ROBERT JOHN ,  FILLION RAYMOND ALBERT ,  KORMAN CHARLES STEVEN ,  ELASSER AHMED ,  BEAUPRE RICHARD ALFRED

    IPC: H01L23/02 ,  H01L21/70 ,  H01L21/768 ,  H01L23/055 ,  H01L23/48

    Abstract: A semiconductor chip packaging structure comprising a dielectric film 1 0 having one or more through holes 11 aligned with the one or more contact pad s 22 and 23 of at least one power semiconductor chip 21. A patterned electrically conductive layer 40 adjacent to the dielectric film 10 has one or more electrically conductive posts 41 which extend through the one or more though holes 11 aligned with the contact pads 22 and 23 to electrically couple the conductive layer 40 to the contact pads 22 and 23. In certain embodiments, one or more air gaps 91 may be formed betwee n the dielectric film 10 and the active surface 24 of the at least one power semiconductor chip 21. Methods for fabricating the semiconductor chip packaging structure are also disclosed.

Patent Agency Ranking